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qt1f- plus device quad t1 framer- plus TXC-03103C document number: preliminary TXC-03103C-mb, ed. 3 october 2004 ? d4 sf, esf (including hdlc link support), and transparent framing modes encodes/decodes ami/b8zs and forced ones density line codes fractional t1 gapped clock monitor function for frame pulse, clock and data two-frame slip buffers in both receive and transmit directions supports channel associated and robbed-bit signaling (enabled or processor forced on a per ds0 basis) detects and forces yellow and ais alarms; detects oof, severely errored frame, and change of frame alignment, detects ais-ci detects, counts and forces line code errors (bpvs and excess zeros), crc errors (esf only), and frame bit errors motorola/intel compatible microprocessor interface one-second interrupt input latches counter values and line events into shadow registers local, line remote, payload remote and ds0 channel loopbacks, per ds0 channel inversion processor forcing/monitoring of ds0s for maintenance purposes boundary scan capability (ieee 1149.1) single +3.3 volt or +5.0 volt power supply 128-pin low profile plastic quad flat package the qt1f- plus (TXC-03103C) is a four-channel ds1 (t1, 1.544 mbit/s) framer designed with extended features for voice and data communications applications. ami, b8zs, and nrz line codes are supported with full alarm detection and generation per ansi t1m1.3. the transmit and receive sections of each of the four framers are independent, with individual slip buffers to allow operation in a wide range of switching and transmission products. d4 sf and esf modes are provided per ansi t1.403-1998 and at&t pub 62411, with per ds0 signaling and ds0 data access and control via a motorola/intel-compatible microprocessor interface. for esf applications, each framer supplies a full duplex hdlc/bit-oriented message controller, supporting back-to-back fdl messages in addition to onboard latching of all required performance parameters; minimal software overhead is required to support either ansi t1.403-1998 or at&t pub 54016 protocols. diagnostic, test, and maintenance functions are provided, including four loopback modes and boundary scan (ieee 1149.1). sonet/sdh terminal or add/drop multiplexers supporting ds1 byte synchronous operation dcs, digital central office or remote digital terminals t1 multiplexers t1 and fractional t1 csus atm products with integrated ds1 interfaces lan routers with integrated ds1 interfaces multichannel ds1 test equipment internet access equipment with t1 and fractional t1 interfaces qt1f- plus TXC-03103C nrz data and signaling highways quad t1 framer- plus ds1 dual rail / nrz data & clocks transceiver serial interface microprocessor interface system & fallback clocks ieee 1149.1 (jtag) interface system (terminal) side line side interrupt/select 4 x 3 4 x 3 4 x 2 4 x 4 4 x 4 system i/o clocks u.s. patent no. 5,615,237 and 6,456,595 copyright ? 2004 transwitch corporation phast, temx28, transwitch and txc are registered trademarks of transwitch corporation mvip is a registered trademark of go-mvip, inc. data sheet proprietary transwitch corporation information for use solely by its customers preliminary information documents contain information on products in the sampling, pre-production or early production phases of the product life cycle. characteristic data and other specifications are subject to change. contact transwitch applications engineering for current information on this product. applications description features transwitch corporation ? 3 enterprise drive shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com
- 2 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers table of contents section page quad t1 framer- plus features ............................................................................................................. 4 block diagram ................................................................................................................. ......................... 6 block diagram description ..................................................................................................... ................. 7 pin diagram ................................................................................................................... ......................... 10 pin descriptions .............................................................................................................. ....................... 11 absolute maximum ratings and environmental limitations .............................................................. 20 thermal characteristics ....................................................................................................... .................. 20 power requirements ............................................................................................................ ................. 21 input, output and input/output parameters ..................................................................................... ... 22 parameters for +3.3 volts supply voltage ................................................................................... 22 parameters for +5.0 volts supply voltage ................................................................................... 24 operation ..................................................................................................................... ........................... 49 line interface selection ...................................................................................................... ............ 49 line interface control ........................................................................................................ ............. 51 monitor mode .................................................................................................................. ................ 52 system interface .............................................................................................................. ............... 52 transmission mode ............................................................................................................. ........... 53 mvip mode ..................................................................................................................... ................ 57 fractional t1 mode ............................................................................................................ ............ 59 per ds0 inversion mode ........................................................................................................ ........ 60 framing ....................................................................................................................... .................... 60 signaling ..................................................................................................................... ..................... 68 clocking and synchronization .................................................................................................. ..... 71 ais detection and generation .................................................................................................. ..... 73 ansi rai - ci detector ........................................................................................................ .......... 74 hdlc channel .................................................................................................................. ............. 74 alarms ........................................................................................................................ ...................... 77 maintenance ................................................................................................................... ................ 79 boundary scan ................................................................................................................. .............. 82 reset procedure ............................................................................................................... .............. 88 memory map .................................................................................................................... ...................... 89 per channel control and status indication registers ................................................................. 91 memory map descriptions ....................................................................................................... ............. 98 application diagram ........................................................................................................... .................. 148 package information ........................................................................................................... ................. 149 ordering information .......................................................................................................... .................. 151 related products .............................................................................................................. .................... 151 standards documentation sources ............................................................................................... .... 152 list of data sheet changes .................................................................................................... ............ 154 please note that transwitch provides documentation for all of its products. current editions of many documents are available from the products page of the transwitch web site at www.transwitch.com . customers who are using a transwitch product, or planning to do so, should register with the tran- switch marketing department to receive relevant updated and supplemental documentation as it is is- sued. they should also contact the applications engineering department to ensure that they are provided with the latest available information about the product, especially before undertaking develop- ment of new designs incorporating the product.
- 3 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers list of figures figure page 1. qt1f- plus TXC-03103C block diagram ........................................................................... 6 2. qt1f- plus TXC-03103C pin diagram ............................................................................. 10 3. dual unipolar (rail) receive interface timing ................................................................. 26 4. dual unipolar (rail) transmit interface timing ................................................................ 27 5. nrz receive interface timing (external transceiver) .................................................... 28 6. nrz transmit interface timing (external transceiver) ................................................... 29 7. nrz receive interface timing (fast sync mode) ........................................................... 30 8. nrz transmit interface timing (fast sync mode) ......................................................... 31 9. serial port write timing ................................................................................................... 32 10. serial port read timing ................................................................................................... 33 11. monitor mode timing ....................................................................................................... 34 12. receive highway timing - transmission mode (recovered receive line clock) .......... 35 13. receive highway timing - transmission mode (system clock) ..................................... 36 14. transmit highway timing - transmission mode .............................................................. 37 15. receive highway timing - mvip mode ........................................................................... 38 16. transmit highway timing - mvip mode .......................................................................... 39 17. receive highway timing - fractional t1 gapped clock (transmission mode) ............... 40 18. transmit highway timing - fractional t1 gapped clock (transmission mode) .............. 41 19. shadow register timing .................................................................................................. 4 2 20. boundary scan timing .................................................................................................... 4 3 21. intel microprocessor read cycle timing ......................................................................... 44 22. intel microprocessor write cycle timing ......................................................................... 45 23. motorola microprocessor read cycle timing .................................................................. 46 24. motorola microprocessor write cycle timing .................................................................. 47 25. clock reference timing .................................................................................................. 4 8 26. line interface for dual unipolar mode ............................................................................ 49 27. line interface for nrz mode .......................................................................................... 50 28. transceiver serial input/output timing ........................................................................... 51 29. transmit highway - transmission mode .......................................................................... 54 30. receive highway - transmission mode ........................................................................... 56 31. transmit highway - mvip mode ...................................................................................... 58 32. receive highway - mvip mode ....................................................................................... 59 33. d4 sf framing structure ................................................................................................. 6 1 34. esf framing structure .................................................................................................... 62 35. transmit slip buffer ...................................................................................................... ... 66 36. receive slip buffer ....................................................................................................... ... 67 37. receive signaling buffer ................................................................................................. 69 38. transmit signaling buffer ................................................................................................ 70 39. hdlc format ............................................................................................................... .... 74 40. shadow register operation ............................................................................................. 79 41. local loopback ............................................................................................................ .... 80 42. remote line loopback .................................................................................................... 8 0 43. payload remote loopback .............................................................................................. 81 44. boundary scan schematic .............................................................................................. 83 45. qt1f- plus TXC-03103C application ............................................................................. 148 46. qt1f- plus TXC-03103C 128-pin package diagram ..................................................... 149 47. qt1f- plus TXC-03103C 128-pin package dimensions ............................................... 150
- 4 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers quad t1 framer- plus features the quad t1 framer- plus device (qt1f- plus , TXC-03103C, see note on next page) is a highly-featured four- channel ds1 (t1) framer for use in a wide variety of interface, transmission and switching applications. four independent ds1 framers are provided in a single monolithic vlsi device using sub-micron cmos technology. powered from a single +5.0 volt supply, the four framers dissipate less than a watt typically. powered from a single +3.3 volt supply, the four framers dissipate less than one third of a watt typically. the qt1f- plus is provided in a rectangular 128-pin low profile plastic quad flat package. its ambient operating temperature range extends from -40 c to +85 c. the qt1f- plus device has been designed to meet the latest industry standards, namely: ansi t1.403-1998 and t1m1.3-005r1 (april 1993) bellcore gr-499-core (issue 1) at&t pub. 62411 (dec. 1990) and pub. 54016 ieee 1149.1- 1990, -1994 mvip (multi-vendor integration protocol) the following features are independently selectable for each of the four ds1 framers: framing modes: d4 sf (superframe format) - programmable for fs, ft or both frame bits esf (extended superframe format) - fps bits with or without a valid crc-6 unframed (bypass) t1dm and other sf modes with external logic line codes: ami b8zs ami with forced ones density nrz (bypass) selectable polarity (nrz) and clock edges signaling: a, ab, 9-state ab signaling for ansi t.403 rob and limited support for slc-96 applications (sf) a, ab, abcd (esf) per ds0 enable with microprocessor read and substitution in both receive and transmit directions for call control and trunk conditioning signaling freeze on los clock management: flexible receive and transmit clock selection, including local oscillator two frame slip buffers for each of receive and transmit paths, with independent bypass system side and line side clocks on receive and transmit, each independent alarms and errors: detect and force yellow and blue (ais) alarms, detect ais-ci signature detect out of frame, loss of signal, severely errored frame, change of frame alignment, transmit slips and receive slips detect, count and force crc errors (esf only), frame bit errors and line code errors (bipolar violations, with or without excessive zeros) detect and force frame slips
- 5 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers fractional t1: gapped clock programmed ds0 channels receive and transmit gapped clocks with selection and direction independent ds0 control: per ds0 enable (independent receive and transmit) with microprocessor read and substitution in both receive and transmit directions per ds0 inversion in transmit and receive directions (after slip buffer) in both transmission and mvip modes . maintenance: loopbacks - line remote, local, payload remote (esf only) and ds0 channel detect and transmit sf loop-up and loop-down codes full duplex hdlc link controller with bit-oriented code support for hdlc link and 16-byte receive and transmit fifos, back-to-back message support boundary scan (ieee 1149.1) for input/output pin monitoring microprocessor interface: eight-bit status register for los, ais, oof, yel, cfa, sef, txslip and rxslip eight-bit latched event register and interrupt mask register crc (esf only), code violation and frame bit error counters shadow registers and counters full control of framing, alarm generation and propagation, codec features hdlc link control, signaling access/control, ds0 access/control reset, resync, slip buffer and frame bit access the following features are only selectable for the four framers as a group: transmission mode ("off line" framing) or mvip mode system interfaces serial port to read/write control up to four line interface transceivers, or selection of one of four ds1 line interfaces (receive or transmit) to monitor clock, frame pulse and data microprocessor global reset, masks, polling registers, interrupt polarity and latch edge control two reference clock outputs at 8khz or 1544 khz with freeze on los ieee 1149.1 boundary scan motorola or intel microprocessor access with separate address and data buses ability to tristate all outputs for in-circuit testing ability to place line side transmit clock and data to logic low for protection switching synchronization start position is programmable to any receive or transmit bit position on the system side external shadow register clock input pseudo-random binary sequence (prbs) generator and analyzer enhancements over the quad t1 framer- plus txc-03103: sf mode 9-state signaling for ansi t-403 rob and limited support for slc-96 applications per ds0 inversion in transmission and mvip modes frame bits available in mvip mode, and supports bypass fdl feature in mvip mode ais-ci detector fdl back-to-back message support
- 6 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers block diagram figure 1. qt1f- plus TXC-03103C block diagram receive slip buffer transmit slip buffer receive framer transmit framer receive signaling transmit signaling hdlc transmit line interface receive line interface framer #1 8 8 8 8 8 8 prbs generator prbs analyzer receive transmit line side system (terminal) side rsync1 rclk1 rdata1 rsigl1/rft1gc1 tsigl1/tft1gc1 tdata1 tclk1 tsync1 clkref1 clkref2 prbsool moto dat(7-0) addr(11-0) sel wr rd , rd/wr rdy/dtack int/irq line interface control lo cso config(2-1) t1si rpos1/rldat1 rneg1/rlbpv1 lrclk1 tpos1/tldat1 tneg1/tmode1 ltclk1 lcs1 lint1 rposn/rldatn rnegn/rlbpvn lrclkn tposn/tldatn lsclk/monclk lsdo/mondto lsdi/monfrm ieee 1149.1 scan i/o: tck tms tdi tdo trs iotri scan_enb rdatan rclkn rsyncn rsigln/rft1gcn tsigln/tft1gcn tdatan tclkn tsyncn (n=2-4) reset sysclk p i/o interface test access port framer #2 framer #3 framer #4 tnegn/tmoden ltclkn lcsn lintn (n=2-4) framer (channel) blocks (4)
- 7 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers block diagram description a simplified block diagram of the quad t1 framer- plus (qt1f- plus ) is shown in figure 1 . the qt1f- plus consists of the following major blocks: four framer blocks, line interface control, prbs generator, prbs analyzer, microprocessor input/output interface, and test access port. each of the four identical framer blocks consists of the following blocks: receive and transmit line interface blocks, receive and transmit framer blocks, hdlc block, receive and transmit slip buffer blocks, and receive and transmit signaling blocks. the receive and transmit line interface blocks connect each of the four framers to an external line interface transceiver, which performs the liu and clock recovery functions. the interface to the external line interface transceiver can be config- ured for two interface modes: a dual unipolar (rail) interface or a nrz interface. when the dual unipolar interface mode is selected, input data from the external line interface transceiver is clocked into the qt1f- plus on pins rposn and rnegn using the recovered receive clock present on the lrclkn input pin (where n=1-4 identifies one of the four framers). in the transmit direction, unipolar data is clocked out of the qt1f- plus on pins tposn and tnegn by the transmit line clock present on the ltclkn output pin. for reduced power dissipation in protec- tion switching applications, the ltclkn, tposn, and tnegn pins for the four framers may be forced low, by placing a low on the cso pin. control bits are provided in the memory map which enable the unipolar data to be clocked in and out of the qt1f- plus on either edge of the clocks. for the dual unipolar interface mode, the qt1f- plus provides either a bipolar with eight zero substitution (b8zs), or an alternate mark inversion (ami), coder and decoder function, and loss of signal detection. the loss of signal detector meets the requirements specified in the ansi t1m1.3 document listed above in the qt1f- plus features section. a sixteen-bit performance counter is provided for each framer, for counting b8zs coding violation errors. an option is provided to also count excessive zeros in the coding violations counter. when the nrz interface mode is selected, nrz data is clocked in at the rldatn pin by the recovered received clock present on the lrclkn pin. the nrz data is clocked out of the qt1f- plus on the tldatn pin by the transmit system clock present on the ltclkn pin. control bits are provided in the memory map which enable the nrz data to be clocked in and out of the qt1f- plus on either edge of the clocks. in nrz interface mode, the b8zs or ami coder and decoder functions are bypassed. however, bipolar violations which are detected in the external line interface transceiver may be clocked into the qt1f- plus on the rlbpvn pin and counted in the associated 16-bit coding violation performance counter. the remote line loopback function for each framer is also implemented in the line interface blocks. the receive framer block for each framer performs frame synchronization alignment. the frame synchronization circuit has framing option for the sf and esf formats. for the sf format, fs or ft, or fs and ft bits can be used for frame align- ment. for the esf format, fps, or fps and a valid crc-6, may be used. the frame synchronizing circuit meets the framing requirements specified in the ansi documents. the out of frame alarm criteria can be programmed to use 2 out of 4, 5, or 6 framing bits in error. framing bit errors and crc-6 errors are counted in performance counters. the receive framer block also monitors and detects the yellow alarm for either the sf or esf formats. a non-framing mode can be enabled when the qt1f- plus is configured in the transmission modes. the non-framing mode bypasses the receive framer block and the receive slip buffer block. when frame alignment is acquired, the signaling bits are forwarded to the receive signaling block for buffering, micropro- cessor access, and formatting into the signaling highway data stream.
- 8 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers each receive slip buffer block controls time slot access and retiming for framer n by using a two-frame receive slip buffer that can be optionally bypassed in the transmission mode. when the receive slip buffer is enabled, received time slots are written into the buffer by recovered receive clock lrclkn, and read out as data (rdatan) from the receive slip buffer by the system input clock rclkn. a phase shift between the two clocks is detected in this block and a deletion or repeti- tion of one frame of data (24 ds0 channels) is provided when the buffer reaches an almost full or almost empty condition, respectively. microprocessor access to the read and write pointers is also provided. the framing bits and signaling bits are not affected by a slip. slip alarm indications are provided for the microprocessor. the receive slip buffer may be recen- tered by the microprocessor, or automatically. individual time slots can be accessed by the microprocessor for the inser- tion of system idle or out of service codes. when the receive slip buffer is bypassed, the receive clock (rclkn) and data (rdatan) are provided as outputs, along with a receive sync signal (rsyncn). for 2, 4 or 16-state signaling (robbed-bit signaling), a 96-bit signaling buffer is used to store the signaling bits which have been extracted by the receive framer. the signaling buffer may be read, frozen and written to by the microprocessor. this feature permits both signaling to or from the microprocessor (call control) as well as trunk conditioning under control of the microprocessor. if signaling is disabled for a particular channel, the abcd signaling bits for that time slot will be fr o- zen in their present states. when a loss of signal or an out of frame condition is detected, the signaling bits are also auto- matically frozen in their present states. the signaling bit states are held until framing has been recovered. nine-state ab signaling for ansi t.403 rob is also supported. on the terminal side, the system interface interconnects the four framers with the system. for each framer there is a sep- arate receive and transmit highway for the transmission and mvip interface modes of operation. the receive highway consists of a data bus (rdatan), a signaling bus (rsigln), a clock (rclkn), and a synchronization signal (rsyncn). the transmit highway consists of a data bus (tdatan), a signaling bus (tsigln), a clock (tclkn), and a synchroniza- tion signal (tsyncn). in the transmission mode, the system interface operates at 1.544 mhz, with channels in the data highway, and signaling and alarms on the signaling highway. the receive and transmit system interfaces are synchro- nized by multiframe pulses that occur at 3-millisecond intervals. twenty-four frames are sent on the data and signaling highways within the 3-millisecond period, with each of the twenty-four frames consisting of 193 bits (24 ds0 channels plus the framing bit), which correspond to a ds1 frame. the receive and transmit slip buffers can be individually bypassed in this mode. when the mvip mode is selected, the system interface also consists of receive and transmit data highways. however, the receive and transmit system interfaces are synchronized by pulses occurring at 125-microsecond intervals in this mode. the receive and transmit slip buffers must always be enabled in this mode. each frame consists of 32 time slots which carry the ds0 channels in defined time slots on the data highway. the signaling highway also carries 32 time slots, which contain the signaling states for each channel. a transmit slip buffer is provided to absorb low speed jitter in the transmit data. each transmit slip buffer block controls time slot access and retiming for the framer by using a two-frame buffer that can be optionally bypassed in the transmis- sion mode. when the transmit slip buffer is enabled, transmit time slots are written into the buffer by the transmit system clock (tclkn), and they are read out from the buffer by the receive clock (lrclkn), local oscillator (lo), or transmit sys- tem clock (tclkn). a phase shift between the two clocks is detected in this block, and a deletion or repetition of one frame of data (i.e., 24 ds0 channels) is provided when the buffer reaches an almost full or almost empty condition, respectively. microprocessor access to the read and write pointers is also provided. buffer alarm indications are also pro- vided. the slip buffer may be recentered by the microprocessor, or automatically. individual time slots can be accessed by the microprocessor for the insertion of system idle or out of service codes. the transmit framer block forms the frame (sf or esf formats) with ds0 channels read from the transmit slip buffer block, and signaling information from the transmit signaling block. the hdlc bits (d-bits) in the esf format can be inserted from the hdlc block or from the system interface (in transmission mode only). a 16-bit code word message provided by the microprocessor can also be inserted into the data bits. the crc-6 is calculated and inserted for the esf format. the yellow alarm indication is inserted by the microprocessor, or via the signaling highway (tsigln). yellow alarm for sf format, and loop-up and loop-down codes, can be inserted, if selected. a single frame bit error, or crc-6 error, can be generated for test purposes. the transmit framer and transmit slip buffer can be bypassed if the unframed mode of operation is selected in the transmission mode.
- 9 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers each framer has a full duplex hdlc link controller. the hdlc link controller can be configured to send and receive mes- sages using the 4 kbit/s d-bits in the esf format. a 16-byte fifo is provided in each direction. interrupt and status alarm support is provided to facilitate fifo servicing for long messages. the hdlc link controller supports zero bit stuffing/ destuffing, itu-t crc generation/checking, flag generation/detection, abort generation/detection, start of frame detec- tion, end of frame detection, and fifo underflows and overflows. the line interface control block provides a serial port for communicating with an external line interface transceiver. this allows the system microprocessor to control the transceiver through the qt1f- plus . the interface consists of a data out- put pin (lsdo), clock output pin (lsclk), and a data input pin (lsdi). these signals are shared between all of the trans- ceivers. each transceiver is selected by the qt1f- plus , using individual chip select output signals (lcsn ). in addition, a general purpose input pin (lintn) can be used to generate a maskable interrupt. the test access port block includes a five-pin test access port (tap) that conforms to the ieee 1149.1 standard. this test access port block provides external boundary scan to read and write the qt1f- plus input and output pins from the tap for board and component testing. in addition, a four-byte read only memory location is provided for reading the tran- switch manufacturer id, a five-digit part identification number, and a version number for the part. to assist in testing, built-in pseudo random binary sequence (prbs) generator and analyzer blocks are provided. the prbs generator and analyzer support a 2 15 -1 bit pseudo random binary sequence which is inverted relative to the pattern specified in the itu-t recommendation o.151. each framer may select the prbs generator and analyzer. the output of the analyzer is provided on pin prbsool. the prbs framed mode, in which the transmit framer generates framing, is selected by writing a 1 to bit 6 in register 013h (prbsfr) and is intended for use as a self-test feature. in this mode, the prbs generator and analyzer can only communicate and frame up within the framer itself. the recovered line clock is the clock source for the analyzer. if the receive slip buffer is enabled, then lrclk must be its read clock source. the lo pin is the clock source for the generator. in unframed prbs mode, which is selected by writing a 0 to prbsfr, the transmit framer does not generate framing. the qt1f- plus also provides local loopback, remote line loopback, payload remote loopback, automatic remote line loopback (based on loop-up/down patterns received over a 5 second period), and ds0 channel loopback options for each framer. the qt1f- plus can be configured to operate with either intel or motorola compatible microprocessors via the micropro- cessor input/output interface block. interrupt capability is provided with global and individual framer mask bits. an option is provided in software which permits the interrupt polarity to be inverted. an external system clock is used to run the inter- nal state machines.
- 10 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers pin diagram figure 2. qt1f- plus TXC-03103C pin diagram addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 dat0 dat1 gnd addr11 vdd dat2 dat3 dat4 dat5 gnd dat6 dat7 int/irq sel wr gnd rd ,rd/wr rdata1 t1si lo config2 config1 gnd vdd clkref1 prbsool iotri scan_enb gnd cso gnd tck tdo tdi trs vdd tms lsdi/monfrm lsclk/monclk rpos1/rldat1 rneg1/rlbpv1/rfs1 lsdo/mondto lint1 addr1 addr0 sysclk moto lcs4 lt c l k 4 tneg4/tmode4/tfs4 tpos4/tldat4 lrclk4 rpos4/rldat4 lint4 gnd rneg4/rlbpv4/rfs4 vdd lcs3 lt c l k 3 tneg3/tmode3/tfs3 tpos3/tldat3 gnd lrclk3 rneg3/rlbpv3/rfs3 lint3 vdd ltclk2 rpos3/rldat3 lcs2 tneg2/tmode2/tfs2 tpos2/tldat2 lrclk2 gnd rneg2/rlbpv2/rfs2 rpos2/rldat2 lint2 lcs1 tneg1/tmode1/tfs1 lrclk1 lt c l k 1 tpos1/tldat1 reset clkref2 tsync4 tclk4 tsigl4/tft1gc4 tdata4 rsync4 rclk4 rsigl4/rft1gc4 tsync3 tclk3 rdy/dtack rdata4 vdd tsigl3/tft1gc3 tdata3 rsync3 rclk3 rsigl3/rft1gc3 gnd rdata3 tclk2 vdd tdata2 tsync2 tsigl2/tft1gc2 rsync2 rclk2 rsigl2/rft1gc2 gnd rdata2 tsync1 tclk1 tsigl1/tft1gc1 rsync1 rsigl1/rft1gc1 tdata1 rclk1 96 95 94 93 92 91 90 83 82 81 80 79 78 77 70 69 68 67 66 65 45 46 47 49 50 51 58 59 60 61 62 63 64 76 75 74 73 72 71 89 88 87 86 85 84 102 101 100 99 98 97 52 53 54 55 56 57 39 40 41 42 43 44 122 121 120 119 118 117 116 109 108 107 106 105 104 103 115 114 113 112 111 110 128 127 126 125 124 123 48 1 2 3 4 5 6 7 8 9 10 11 12 13 20 21 22 23 24 25 26 33 34 35 36 37 38 14 15 16 17 18 19 27 28 29 30 31 32 14 (top view) pin diagram qt1f- plus TXC-03103C note: this diagram is rotated relative to the top view shown in the package diagram in figure 46a.
- 11 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers pin descriptions power supply and ground * note: i = input; o = output; p = power; t=tristate. line interface signals symbol pin no. i/o/p* type name/function vdd 14, 25, 45, 57, 78, 89, 116 p power supply: +3.3 or +5.0 volt, 5%, v dd supply voltage. gnd 20, 30, 44, 47, 52, 73, 84, 94, 111, 121, 124 p ground: 0 volt reference. symbol pin no. i/o/p type * name/function rposn/ rldatn (n=4-1) 91 81 71 63 ittl receive unipolar positive signal input: when control bit rail (bit 7 in register x00h) is a 1, the dual unipolar (positive/negative rail) mode is selected, and the rposn pin carries the receive positive rail input signal. rposn is high whenever a positive pulse is received by the external line interface transceiver. receive line (nrz) data input: when control bit rail (bit 7 in reg- ister x00h) is a 0, the nrz mode is selected, and the rldatn pin carries the receive nrz data input signal. rldatn is normally active high whenever a positive or negative pulse is received by the external line interface transceiver. when control bit rxnrzp (bit 0 in register x01h) is a 1, the qt1f- plus accepts an inverted data signal and rldatn is active low. rnegn/ rlbpvn/ rfsn (n=4-1) 92 82 72 64 ittl receive unipolar negative signal input: when control bit rail (bit 7 in register x00h) is a 1, the dual unipolar (positive/negative rail) mode is selected, and the rnegn pin carries the receive negative rail input signal. rnegn is high whenever a negative pulse is received by the external line interface transceiver. external receive bipolar violation indication input: when control bit rail (bit 7 in register x00h) is a 0 and the fast sync option is not selected (control bit rxfs, bit 1 in register x06h, is a 0), the rlbpvn pin provides an input for indications of external bipolar violations detected in the external line interface transceiver. a high indicates a bipolar violation, and increments the internal 16-bit coding violation counter once on a clock cycle. a bipolar violation is clocked in on rising edges of the receive line clock lrclkn. receive fast sync: when control bit rail (bit 7 in register x00h) is a 0 and the fast sync mode is selected (control bit rxfs, bit 1 in reg- ister x06h, is a 1), this pin is used for a fast sync feature. a pulse on this pin is interpreted as identifying bit 192 of the last frame of the multiframe. * note: see input, output and input/output parameters section for type definitions, which depend on the value of v dd selected.
- 12 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers lrclkn (n=4-1) 93 83 74 65 ittl receive line clock: an input for the 1544 khz recovered clock from the external line interface transceiver. control bit rxcp (bit 6 in regis- ter x01h) determines the clock edge on which the receive line sig- nals rposn/rnegn and rldatn are to be clocked in (1 for rising edge). tposn/ tldatn (n=4-1) 95 85 75 66 o cmos 2ma transmit unipolar positive signal output: when control bit rail (bit 7 in register x00h) is a 1, the dual unipolar mode is selected, and the tposn pin carries the transmit positive rail output signal. tposn is high whenever a positive pulse is to be transmitted by the external line interface transceiver. transmit line (nrz) data output: when control bit rail (bit 7 in register x00h) is a 0, the nrz mode is selected, and the tldatn pin carries the transmit nrz data output signal. tldatn is normally active high whenever a positive or negative pulse is to be transmitted by the external line interface transceiver. when control bit txnrzp (bit 5 in register x01h) is a 1, the data output tldatn is inverted and it is active low. tnegn/ tmoden/ tfsn (n=4-1) 96 86 76 67 o cmos 2ma transmit unipolar negative signal output: when control bit rail (bit 7 in register x00h) is a 1, the dual unipolar mode is selected, and the tnegn pin carries the transmit negative rail output signal. tnegn is high whenever a negative pulse is to be transmitted by the external line interface transceiver. transmit mode general purpose output: when control bit rail (bit 7 in register x00h) is a 0 and the fast sync mode is not selected (control bit txfs, bit 0 in register x06h, is a 0), the state written into bit be (bit 6 in register x00h) is clocked out on rising edges of the transmit line clock ltclkn. transmit fast sync: when control bit rail (bit 7 in register x00h) is a 0 and the fast sync mode is selected (control bit txfs, bit 0 in register x06h is a 1), this pin is used for a fast sync feature providing a sync pulse every 3 ms whether in sf or esf mode; a pulse is sent on this pin for bit 192 in frame 24 when the esf framing mode is selected and every other frame number 12 when the sf framing mode is selected. the esf mode is selected when control bits fmd1 and fmd0 (bits 2-1 in register x04h) are set to 11. the sf mode is selected when the fmd1 and fmd0 bits are written with 01. lt c l k n (n=4-1) 97 87 77 68 o cmos 2ma transmit line clock: a 1544 khz clock output. control bit txcp (bit 7 in register x01h) determines the clock edge on which the transmit line signals tposn/tnegn and tldatn are to be clocked out (1 for rising edge). symbol pin no. i/o/p type * name/function
- 13 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers line interface control signals symbol pin no. i/o/p type name/function lintn (n=4-1) 90 80 70 62 ittl general purpose interrupt input port: when enabled by control bit lie (bit 1 in register x00h) being set to 1, the sig- nal on this pin is logically or-gated with the internal loss of signal indication to cause a loss of signal alarm and (if enabled) an interrupt. control bit lpol (bit 0 in register x00h) selects the input sense of this pin (1 for active low). this pin is active in both dual unipolar and nrz modes. lcsn (n=4-1) 98 88 79 69 o cmos 2ma line interface transceiver chip select: an active low sig- nal that enables communications in both directions between the external line interface transceiver for channel n and the qt1f- plus . lsclk/ monclk 61 o(t) cmos 2ma line interface transceiver clock signal: the clock for the transceiver is enabled when the config2 pin (pin 42) is low. this clock is shared between the four external transceivers. it is used to clock input data, and output data, between the external line interface transceiver and the qt1f- plus . this clock is derived from the signal at pin lo. output data (lsdo) is clocked out of the qt1f- plus on falling edges of this clock. input data (lsdi) is clocked into the qt1f- plus on rising edges of this clock. monitor clock signal: the monitor feature is enabled when the config2 pin (pin 42) is high. the monclk pin provides either a receive or transmit nrz clock. the clock in this mode can be tristated by writing a 0 to control bit esp/emon (bit 4 in register 013h). lsdo/ mondto 60 o(t) cmos 2ma line interface transceiver data output signal: the output data signal for the transceivers is enabled when the config2 pin (pin 42) is low. the output data signal is shared between the four transceivers. monitor data signal: the monitor feature is enabled when the config2 pin (pin 42) is high. the mondto pin pro- vides either a nrz receive or transmit data signal. this pin can be tristated in this mode by writing a 0 to control bit esp/ emon (bit 4 in register 013h). lsdi/ monfrm 59 i/o ttl/cmos 4ma line interface transceiver data input signal: the input data signal from the transceivers is enabled when the config2 pin (pin 42) is low. the input data signal is shared between the four transceivers. monitor frame: this pin becomes an output when the config2 pin is high and a 1 is written to control bit enmonfr (bit 2 in register 013h). this bit is active high during the bit time of bit 192 and low during other bit times. the frame pulse is clocked out on the rising edges of monclk.
- 14 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers clock reference signals system interface signals symbol pin no. i/o/p type name/function clkref1 46 o(t) cmos 2ma clock reference 1: this clock reference output is enabled when control bit enref1 (bit 3 in register 019h) is a 1. the clock refer- ence signal can be either a 1544 khz clock or an 8 khz clock. when control bit 1544khz (bit 4 in register 019h) is a 1, the 1544 khz reference is selected. the framer from which the clock is derived is determined by selection bits cr1s1 and cr1s0 (bits 1 and 0 in register 019h). this pin is forced low when a loss of sig- nal alarm occurs for the framer selected. clkref2 2 o(t) cmos 2ma clock reference 2: this clock reference output is enabled when control bit enref2 (bit 5 in register 019h) is a 1. the clock refer- ence signal can be either a 1544 khz clock or an 8 khz clock. when control bit 1544khz (bit 4 in register 019h) is a 1, the 1544 khz reference is selected. the framer from which the clock is derived is determined by selection bits cr2s1 and cr2s0 (bits 7 and 6 in register 019h). this pin is forced low when a loss of sig- nal alarm occurs for the framer selected. symbol pin no. i/o/p type name/function tsyncn (n=4-1) 3 12 22 32 ittl transmit sync pulse : this signal is used to synchronize both the frame sync and signaling multiframe sync counters within a qt1f- plus framer and is sourced by the system. the following table is a summary of the sync pulse characteristics used for the various system interfaces. interface width polarity period lead used transmission 1 clk cyc high 3 ms tsyncn mvip 1 clk cyc low 125 stsyncn please note: the sync pulse is also programmable with respect to the transmit data highway. tclkn (n=4-1) 4 13 23 33 ittl transmit clock: this clock is sourced from the system. it is used to clock in the tsyncn, tsigln, and tdatan signals from the system. the following table is a summary of the clock rates and clock transitions used for clocking in data (d), signaling (s), and the sync pulse. clk in clk in interface rate d/s sync l lead used transmission 1.544 mhz pos. pos. tclkn mvip 2.048 mhz neg. pos. tclkn
- 15 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers tdatan (n=4-1) 6 16 26 35 ittl transmit data highway input: this lead carries the data time slots from the system interface to the qt1f- plus . the following table is a summary of the transmit data highway format. interface format transmission ds1 frame (193 bit positions) repeated 24 times on tdatan mvip ds1 frame mapped into 32 time slots on tdatan tsigln/ tft1gcn (n=4-1) 5 15 24 34 i/o ttl/cmos 4ma transmit signaling highway input: this lead carries from the system the signals that represent signaling information and an alarm indication (transmission mode only), according to the table given below. interface format transmission 193-bit frame format repeated 24 times on tsigln mvip 32 time slots on tsigln transmit fractional t1 gapped clock output: the transmit fractional t1 gapped clock feature is enabled when the config1 pin is low (transmission mode) and control bit ft1m (bit 0 in register x02h) is written with a 1. a gapped clock is pro- vided on the pin for the fractional t1 channel(s) selected. one or more ds0 channels may be selected by writing a 1 to control bits tfd1-tfd24 in registers x3dh-x3fh. the gapped clock has the same phase as the tclkn clock. rsyncn (n=4-1) 7 17 27 36 i/o ttl/cmos 4ma receive sync pulse: this signal is used to synchronize external system circuitry from the qt1f- plus . it is an input if the receive slip buffer is enabled, otherwise it is an output. the following table is a summary of the sync pulses used for the various system interfaces. interface width polarity period lead used transmission 1 clk cyc high 3 ms rsyncn mvip 1 clk cyc low 125 srsyncn please note that for the transmission mode, the qt1f- plus can source the sync pulse and clock. the selection of input or output is determined by control bit rxc (bit 5 in register x02h); writing a 0 to rxc causes rsyncn to be an input and writing a 1 to rxc causes rsyncn to be an output. the sync pulse is also pro- grammable with respect to the receive data highway. symbol pin no. i/o/p type name/function
- 16 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers rclkn (n=4-1) 8 18 28 37 i/o ttl/cmos 4ma receive clock: this clock is used to clock the rdatan, rsigln, and rsyncn signals from the system or (for rsyncn) into the system. the following table is a summary of the clock rates and clock transitions used for clocking data (d), signaling (s), and the sync pulse. clk out clk in interface rate d/s sync lead used transmission 1.544 mhz neg. pos. rclkn mvip 2.048 mhz pos. pos. rclkn note: in the transmission mode, rsyncn is clocked out on neg- ative clock transitions when the sync pulse is an output. the selection of input or output is determined by control bit rxc (bit 5 in register x02h); writing a 0 to rxc causes rclkn to be an input and writing a 1 to rxc causes rclkn to be an output. rdatan (n=4-1) 11 21 31 39 o cmos 2ma receive data highway output: this lead carries the time slots from the qt1f- plus to the system. the following table is a sum- mary of the receive data highway format. interface format transmission ds1 frame (193 bit positions) repeated 24 times on rdatan mvip ds1 frame mapped into 32 time slots on rdatan rsigln/ rft1gcn (n=4-1) 10 19 29 38 o cmos 2ma receive signaling highway output: this lead carries to the system the signals that represent signaling information and an alarm indication (transmission mode only), according to the table given below. interface format transmission 193-bit frame format repeated 24 times on rsigln mvip 32 time slots on rsigln receive fractional t1 gapped clock output: the received fractional t1 gapped clock feature is enabled when the config1 pin is low (transmission mode) and control bit ft1m (bit 0 in register x02h) is written with a 1. a gapped clock is pro- vided on this pin for the fractional t1 channel(s) selected. one or more ds0 channels may be selected by writing a 1 to control bits rfd1-rfd24 in registers x3ah-x3ch. the gapped clock has the same phase as the rclkn clock. symbol pin no. i/o/p type name/function
- 17 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers other signals lo 41 ittl local oscillator input: this independent 1544 khz 32 ppm (50 10)% duty cycle clock is an alternate clock source for the transmit line clock (ltclkn), and for clocking out data from the slip buffer. this clock is selected as the transmit clock source when control bits txc1 and txc0 (bits 7 and 6 in register x02h) are both set to 0. on the detection of loss of signal, this clock is substituted for the receive line clock (lrclkn) which becomes rclkn when control bit rxc (bit 5 in register x02h) is set to a 1. this clock is required for generating lsclk (pin 61) and the prbs generator function. when used for the prbs generator it must be synchronous with tclkn, where ? n ? is the framer sourc- ing prbs. symbol pin no. i/o/p type name/function t1si 40 i ttl one second shadow register signal : a positive pulse occurring every second which latches the performance counters (crc-6 error, coding violation, and frame bit error) and pm and fm registers when the shadow register feature is enabled. the performance counters can count without this clock present, but they will not be shadowed. to comply with ansi t1.403 this clock should be 1.0 hz 32 ppm. the shadow register feature is enabled when a 1 is written to control bit enpmfm (bit 3 in register 006h). this input is required for automatic loop-up/down code detection. config2 42 i ttl configuration 2 select pin : a low enables the line control inter- face for communications between the qt1f- plus and the exter- nal line interface transceivers. a high disables the line control interface, and configures clock and data pins for a monitor inter- face. the selection is common to all four framers. config1 43 i ttl configuration 1 select pin : a low configures the qt1f- plus for the transmission mode of operation (1544 kbit/s) at the system interface. a high configures the qt1f- plus for the mvip mode of operation at the system interface. the selection is common to all four framers. cso 49 i ttl power down : an active low on this pin forces the transmit clock (ltclkn), and the transmit unipolar leads (tposn and tnegn) for rail data output signals, of all four framers to the active low state for protection switching purposes. prbsool 48 o cmos 2ma prbs out of lock: enabled only in the transmission mode and when control bit prbsen (bit 5 in register 013h) is a 1. a high indicates the analyzer is out of lock. this pin is low when lock is acquired or when this feature is disabled. symbol pin no. i/o/p type name/function
- 18 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers boundary scan microprocessor interface iotri 50 i ttl high z state: an active low placed on this pin forces all output pins (except tdo) to a high impedance state for test purposes. this pin must be held high for normal operation. scan_enb 51 i ttl transwitch test pin: this pin is used for manufacturing tests only and must be held low for normal operation. symbol pin no. i/o/p type name/function tck 53 i ttl ieee 1149.1 test port serial scan clock: this clock is used to shift data in on pin tdi on rising edges, and to shift data out on pin tdo on falling edges. the maximum clock frequency is 10 mhz. tms 58 i ttlp ieee 1149.1 test port mode select: this signal is clocked in on rising edges of the clock tck, and is used to place the test access port controller into various states as defined in the ieee 1149.1 standard. this pin must be high for normal framer opera- tion. tdi 55 i ttlp ieee 1149.1 test port serial scan data in: serial test instruc- tions and data are clocked in to this pin on rising edges of clock tck. tdo 54 o(t) cmos 4ma ieee 1149.1 test port serial scan data out: serial test instruc- tions and data are clocked out of this pin on falling edges of clock tck. when inactive, this output is forced to the high impedance state. trs 56 i ttlp ieee 1149.1 test port reset pin: this pin must either be held low, asserted low, or asserted low then high (pulsed low, 10 ns minimum) to asynchronously reset the test access port (tap) controller. failure to do so may cause the tap controller to take control of the qt1f- plus output pins. symbol pin no. i/o/p type name/function moto 99 i ttl motorola / intel processor select: this pin defines the operating mode of the microprocessor input/output interface. when it is high, motorola (m) mode is selected. when it is low, intel (i) mode is selected. addr(11-0) 113, 112, 110-101 ittl address bus (motorola/intel buses): these pins are address line inputs that are used for accessing a register location for a read/write cycle. high is logic 1. for normal operation addr11 may be tied low. dat(7-0) 123, 122, 120-117, 115, 114 i/o(t) cmos 8ma data bus: bidirectional data lines used for transferring data. high is logic 1. symbol pin no. i/o/p type name/function
- 19 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers sel 127 i ttlp select: a low enables data transfers between the microprocessor and the qt1f- plus during a read/write cycle. rd or rd/wr 126 i ttl read (i mode) or read/write (m mode): intel mode - an active low signal generated by the microprocessor for reading the qt1f- plus register locations. motorola mode - an active high signal generated by the microproces- sor for reading the qt1f- plus register locations. an active low signal is used to write to qt1f- plus register locations. wr 128 i ttl write (i mode): intel mode - an active low signal generated by the microprocessor for writing to the qt1f- plus register locations. motorola mode - not used (should be set high). rdy/dtack 9o(t)cmos 8ma ready (i mode) or data transfer acknowledge (m mode): intel mode - a high is an acknowledgment from the addressed register location that the transfer can be completed. a low indicates that the qt1f- plus cannot complete the transfer cycle, and microprocessor wait states must be generated. motorola mode - during a read bus cycle, a low signal indicates the information on the data bus is valid. during a write bus cycle, a low sig- nal acknowledges the acceptance of data. this lead is tristated after the low signal. int/irq 125 o cmos 4ma interrupt: intel mode - a high on this output pin signals an interrupt request to the microprocessor. motorola mode - a low on this output pin signals an interrupt request to the microprocessor. the interrupt sense is inverted when a 1 is written to control bit ipol (bit 4 in register 006h). reset 1 i ttlp reset: a low placed on this pin resets the qt1f- plus . the reset must be placed on this pin after the clocks become stable, and must have a minimum duration of 10 cycles of the sysclk system clock. sysclk 100 i ttl system clock: this asynchronous clock is used by the qt1f- plus to run the internal state machines and counters. the nominal frequency of this clock is 16.0-19.0 mhz with a duty cycle of (50 10)%. this fre- quency range will provide correct operation with a t1 signal that com- plies with the frequency range and jitter as specified in at&t pub. 62411 or bellcore gr-499-core. when the qt1f- plus is used in a gapped clock situation (e.g., a direct connection to the t1 ports of the m13e device, txc-03303), the sysclk minimum frequency must guarantee that at least 10 rising edges of sysclk occur between any two consecutive rising edges of any particular lrclkn. note: for v dd = +5.0 volts, nominally, the sysclk operating frequency may be extended to 22.0 mhz with a duty cycle of (50 10)% symbol pin no. i/o/p type name/function
- 20 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers absolute maximum ratings and environmental limitations notes: 1. conditions exceeding the min or max values may cause permanent failure. exposure to conditions near the min or max values for extended periods may impair device reliability. 2. pre-assembly storage in non-drypack conditions is not recommended. please refer to the instructions on the "caution" label on the drypack bag in which devices are supplied. 3. v in may not exceed the actual operating supply voltage ( v dd , either +3.3 volts or +5.0v, 5%) by more than 0.5 volts. 4. test method for esd per per jedec jesd22-a114-b. thermal characteristics parameter symbol min max unit conditions supply voltage v dd -0.3 +7.0 v note 1 dc input voltage v in -0.5 v dd + 0.5 v notes 1, 3 storage temperature range t s -55 150 o c note 1 ambient operating temperature range t a -40 85 o c 0 ft/min linear airflow moisture exposure level me 5 level per ipc/jedec j-std-020b relative humidity, during assembly rh 30 60 % note 2 relative humidity, in-circuit rh 0 100 % non-condensing esd classification esd absolute value 2000 v note 4 latch-up lu meets jedec jc 40.2 parameter min typ max unit test conditions thermal resistance: junction to ambient 27.8 o c/w 0 ft/min linear airflow
- 21 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers power requirements +3.3 volts supply voltage +5.0 volts supply voltage parameter min typ max unit test conditions v dd (operating) 3.15 3.30 3.45 v i dd (outputs loaded) 30 1 40 2 ma 1. all channels operating. output load 30 pf. sysclk at 16 mhz. 2. all channels operating. output load 30 pf. sysclk at 19 mhz. p dd (outputs loaded) 100 1 140 2 mw i dd (outputs unloaded) 30 ma all channels operating. output load 0 pf. sysclk at 16 mhz. p dd (outputs unloaded) 100 mw i dd (outputs loaded) 25 ma all channels powered down. output load 30 pf. sysclk at 16 mhz. p dd (outputs loaded) 85 mw parameter min typ max unit test conditions v dd (operating) 4.75 5.0 5.25 v i dd (outputs loaded) 50 1 70 2 ma 1. all channels operating. output load 30 pf. sysclk at 16 mhz. 2. all channels operating. output load 30 pf. sysclk at 22 mhz. p dd (outputs loaded) 250 1 370 2 mw i dd (outputs unloaded) 50 ma all channels operating. output load 0 pf. sysclk at 16 mhz. p dd (outputs unloaded) 265 mw i dd (outputs loaded) 40 ma all channels powered down. output load 30 pf. sysclk at 16 mhz. p dd (outputs loaded) 200 mw
- 22 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers input, output and input/output parameters parameters for +3.3 volts supply voltage input parameters for ttl @ v dd = +3.3v input parameters for ttlp @ v dd = +3.3v output parameters for cmos4ma @ v dd = +3.3v output parameters for cmos8ma @ v dd = +3.3v parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd < 3.45 v il 0.8 v 3.15 < v dd < 3.45 input leakage current 10 av dd =3.45; input = 0 to 3.45 input capacitance 4.1 pf parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd < 3.45 v il 0.8 v 3.15 < v dd < 3.45 input leakage current -0.02 -0.50 ma v dd =3.45; input = 0 volts input capacitance 5.5 pf parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 3.15; i oh = -4.0 v ol 0.4 v v dd = 3.15; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma t rise 10 ns c load = 15 pf t fal l 10 ns c load = 15 pf leakage current, tristate 10 av dd =3.45; input = 0 to 3.45 parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 3.15; i oh = -8.0 v ol 0.4 v v dd = 3.15; i ol = 8.0 i ol 8.0 ma i oh -8.0 ma t rise 10 ns c load = 25 pf t fal l 10 ns c load = 25 pf leakage current, tristate 10 av dd =3.45; input = 0 to 3.45
- 23 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers output parameters for cmos2ma @ v dd = +3.3v input/output parameters for ttl/cmos8ma (slew rate controlled) @ v dd = +3.3v input/output parameters for ttl/cmos4ma @ v dd = +3.3v parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 3.15; i oh = -2.0 v ol 0.4 v v dd = 3.15; i ol = 2.0 i ol 2.0 ma i oh -2.0 ma t rise 10 ns c load = 15 pf t fal l 10 ns c load = 15 pf leakage tristate 10 av dd =3.45; input = 0 to 3.45 parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd < 3.45 v il 0.8 v 3.15 < v dd < 3.45 input leakage current 10 av dd = 3.45 input capacitance 7.0 pf v oh v dd - 0.5 v v dd = 3.3; i oh = -8.0 v ol 0.4 v v dd = 3.3; i ol = 8.0 i ol 8.0 ma i oh -8.0 ma t rise 10 ns c load = 25 pf t fal l 10 ns c load = 25 pf leakage current, tristate 10 av dd =3.45; input = 0 to 3.45 parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd < 3.45 v il 0.8 v 3.15 < v dd < 3.45 input leakage current 10 av dd = 3.45 input capacitance 7.0 pf v oh v dd - 0.5 v v dd = 3.3; i oh = -4.0 v ol 0.4 v v dd = 3.3; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma t rise 10 ns c load = 15 pf t fal l 10 ns c load = 15 pf leakage tristate 10 av dd =3.45; input = 0 to 3.45
- 24 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers parameters for +5.0 volts supply voltage input parameters for ttl @ v dd = +5.0v input parameters for ttlp @ v dd = +5.0v output parameters for cmos4ma @ v dd = +5.0v output parameters for cmos8ma @ v dd = +5.0v parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 av dd =5.25; input = 0 to 5.25 input capacitance 4.1 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current -0.05 -0.50 ma v dd =5.25; input = 0 volts input capacitance 5.5 pf parameter min typ max unit test conditions v oh v dd -0.5 v v dd = 4.75; i oh = -4.0 v ol 0.4 v v dd = 4.75; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma t rise 10 ns c load = 15 pf t fal l 10 ns c load = 15 pf leakage current, tristate 10 av dd =5.25; input = 0 to 5.25 parameter min typ max unit test conditions v oh v dd -0.5 v v dd = 4.75; i oh = -8.0 v ol 0.4 v v dd = 4.75; i ol = 8.0 i ol 8.0 ma i oh -8.0 ma t rise 10 ns c load = 25 pf t fal l 10 ns c load = 25 pf leakage current, tristate 10 av dd =5.25; input = 0 to 5.25
- 25 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers output parameters for cmos2ma @ v dd = +5.0v input/output parameters for ttl/cmos8ma (slew rate controlled) @ v dd = +5.0v input/output parameters for ttl/cmos4ma @ v dd = +5.0v parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 4.75; i oh = -2.0 v ol 0.4 v v dd = 4.75; i ol = 2.0 i ol 2.0 ma i oh -2.0 ma t rise 10 ns c load = 15 pf t fal l 10 ns c load = 15 pf leakage tristate 10 av dd =5.25; input = 0 to 5.25 parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25 input capacitance 7.0 pf v oh v dd - 0.5 v v dd = 4.75; i oh = -8.0 v ol 0.4 v v dd = 4.75; i ol = 8.0 i ol 8.0 ma i oh -8.0 ma t rise 10 ns c load = 25 pf t fal l 10 ns c load = 25 pf leakage tristate 10 av dd =5.25; input = 0 to 5.25 parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25 input capacitance 7.0 pf v oh v dd - 0.5 v v dd = 4.75; i oh = -4.0 v ol 0.4 v v dd = 4.75; i ol = 4.0 i ol 4.0 ma i oh -4.0 ma t rise 10 ns c load = 15 pf t fal l 10 ns c load = 15 pf leakage tristate 10 av dd =5.25; input = 0 to 5.25
- 26 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers timing characteristics detailed timing diagrams for the qt1f- plus are illustrated in figures 3 through 25 , with values of the timing intervals tab- ulated below the waveform diagrams in each figure. all output times are measured with a maximum 25 pf load capaci- tance. timing parameters are measured at voltage levels of (v ih + v il )/2 for input signals or (v oh + v ol )/2 for output signals, unless otherwise indicated. figure 3. dual unipolar (rail) receive interface timing notes: 1. lrclkn is shown for control bit rxcp (bit 6 in register x01h) set to 0. data (rposn/rnegn) is clocked in on the rising edges of lrclkn when control bit rxcp is a 1. 2. the minimum frequency of sysclk must guarantee at least 10 rising edges of sysclk occur between any two consecutive rising edges of any particular lrclkn. parameter symbol min typ max unit lrclkn clock period (see note 2) t cyc 648 ns lrclkn high time t pwh 324 ns lrclkn low time t pwl 324 ns rposn/rnegn set-up time to lrclkn t su 10 ns rposn/rnegn hold time after lrclkn t h 10 ns t su lrclkn rposn (input) rnegn (input) note: n=1, 2, 3, 4 t h t pwh t pwl t cyc (see note 1)
- 27 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 4. dual unipolar (rail) transmit interface timing note: ltclkn is shown for control bit txcp (bit 7) in register x01h set to 1. data is clocked out on falling edges of ltclkn whe n con- trol bit txcp is a 0. parameter symbol min typ max unit ltclkn clock period t cyc 648 ns ltclkn duty cycle (t pwh /t cyc ) -- 455055% tposn/tnegn delay after ltclkn t d 0.0 5.0 15 ns t d ltclkn tposn t cyc (output) tnegn (output) note: n=1, 2, 3, 4 t pwh
- 28 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 5. nrz receive interface timing (external transceiver) notes: 1. lrclkn is shown for control bit rxcp (bit 6 in register x01h) set to 0. rldatn and rlbpvn are clocked in on rising edges of lrclkn when control bit rxcp is a 1. the qt1f- plus accepts an inverted rldatn signal when control bit rxnrzp (bit 0 in register x01h) is a 1. control bit rxfs (bit 1 in register x06h) must be set to 0 to use the rlbpvn input. 2. the minimum frequency of sysclk must guarantee that at least 10 rising edges of sysclk occur between any two consecu- tive rising edges of any particular lrclkn. parameter symbol min typ max unit lrclkn clock period (see note 2) t cyc 648 ns lrclkn high time t pwh 324 ns lrclkn low time t pwl 324 ns rldatn/rlbpvn set-up time to lrclkn t su 20 ns rldatn/rlbpvn hold time after lrclkn t h 20 ns t pwh lrclkn t cyc t pwl (input) t su t h rldatn (input) t su t h rlbpvn (input) note: n=1, 2, 3, 4 external bipolar violation (see note 1)
- 29 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 6. nrz transmit interface timing (external transceiver) note: ltclkn is shown for control bit txcp (bit 7 in register x01h) set to 1. tldatn and tmoden are clocked out on falling edges of ltclkn when control bit txcp is a 0. the qt1f- plus provides an inverted tldatn signal when control bit txnrzp (bit 5 in register x06h) is a 1. control bit txfs (bit 0 in register x06h) must be set to 0 to obtain the tmoden output. parameter symbol min typ max unit ltclkn clock period t cyc 648 ns ltclkn duty cycle (t pwh /t cyc ) -- 455055% tldatn/tmoden delay after ltclkn t d 10 15 20 ns t d ltclkn t cyc (output) tldatn (output) t d tmoden (output) note: n=1, 2, 3, 4 state determined by control bit be (bit 6 in x00h) t pwh
- 30 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 7. nrz receive interface timing (fast sync mode) note: lrclkn is shown for control bit rxcp (bit 6 in register x01h) set to 0. data is clocked in on rising edges when control bi t rxcp is a 1. the qt1f- plus will accept an inverted rldatn signal when a 1 is written to control bit rxnrzp (bit 0 in register x01h). the fast sync mode is selected by writing a 1 to control bit rxfs (bit 1 in register x06h). parameter symbol min typ max unit lrclkn clock period t cyc(1) 648 ns lrclkn high time t pwh(1) 324 ns lrclkn low time t pwl(1) 324 ns rldatn/rfsn set-up time to lrclkn t su 20 ns rldatn/rfsn hold time after lrclkn t h 20 ns rfsn period t cyc(2) 3.0 ms rfsn pulse width high time t pw 1 t cyc(1) ns rldatn lrclkn (input) (input) t pwl(1) t pwh(1) t cyc(1) rfsn (input) t su t h bit 192 bit 0 bit 192 bit 0 t cyc(2) t h t su note: n=1, 2, 3, 4 t pw esf format: frame 24 sf format: every other frame 12
- 31 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 8. nrz transmit interface timing (fast sync mode) note: ltclkn is shown for control bit txcp (bit 7 in register x01h) set to 1. tldatn/tfsn are clocked out on falling edges of lt clkn when control bit txcp is set to 0. the qt1f- plus will output an inverted tldatn signal when control bit txnrzp (bit 5 in regis- ter x06h) is a 1. the fast sync mode is selected by writing a 1 to control bit txfs (bit 0 in register x06h). parameter symbol min typ max unit ltclkn clock period t cyc(1) 648 ns ltclkn duty cycle t pwh(1) /t cyc(1) 45 50 55 % tfsn delay after ltclkn t d 5.0 10 15 ns tfsn pulse width high time t pw 1 t cyc(1) ns tfsn period t cyc(2) 3.0 ms tldatn ltclkn (output) (output) t cyc(1) tfsn (output) bit 192 bit 0 bit 192 t pw t d t cyc(2) frame f+1 frame f note: n=1, 2, 3, 4 t pwh(1) esf format: frame 24 sf format: every other frame 12
- 32 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 9. serial port write timing notes: 1. the serial port interface for the line interface transceiver is selected when an active low is placed on the config2 pin (pin 42). 2. the clock period for lsclk is the same as that of the clock provided on the lo pin (pin 41), since lsclk is derived from the signal at lo. 3. usually, the minimum high time or low time has to be in the order of 290 ns for the part to be able to function over the enti re sysclk range of 16-22 mhz. however, if line clock high or low times fall to 240 ns, the device can only operate satisfactorily with the sysclk at between 20-22 mhz. parameter symbol min typ max unit lcsn pulse width high time t pw 300 ns lsclk clock period (see note 2) t cyc 648 ns lsclk high time (see note 3) t pwh 240 324 408 ns lsclk low time (see note 3) t pwl 240 324 408 ns lcsn delay after lsclk t d(1) 0.0 1.0 5.0 ns lsdo delay after lsclk t d(3) 0.0 1.0 5.0 ns lcsn delay after lsclk t d(2) 0.0 1.0 5.0 ns t pw t d(2) t d(3) t cyc t pwh lsclk t pwl lcsn lsdo (output) (output) (output) t d(1) lsb lsb msb address/command data byte byte note: n=1, 2, 3, 4
- 33 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 10. serial port read timing notes: 1. the serial port interface for the line interface transceiver is selected when an active low is placed on the config2 pin (pin 42). 2. the clock period for lsclk is the same as that of the clock provided on the lo pin (pin 41), since lsclk is derived from the signal at lo. parameter symbol min typ max unit lsdi set-up time to lsclk t su 20 ns lsdi hold time after lsclk t h 20 ns lcsn delay after lsclk t d(1) 20 25 30 ns lcsn delay after lsclk t d(2) 20 25 30 ns t d(2) lsclk lcsn lsdi (output) (output) (input) t d(1) t su t h
- 34 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 11. monitor mode timing note: the monitor port is enabled when an active high is placed on the config2 pin (pin 42). control bits t1chcs1 and t1chcs0 (bits 1, 0 in register 013h) select the channel to be monitored. control bit rxtx (bit 3 in register 013h) selects either the r eceive side or transmit side to be monitored. writing a 0 to control bit esp/emon (bit 4 in register 013h) tristate both outputs. the input signals to the receive framer (mondto and monclk) are monitored when control bit rxtx is a 1 and control bit enmonfr (bit 2 in register 013h) is a 0. when control bits rxtx and enmonfr are equal to 1, the receive framer output is monitored (mondto, monfrm and monclk). parameter symbol min typ max unit monclk clock period t cyc 637 648 700 ns monclk high time t pwh 324 ns monclk low time t pwl 324 ns mondto delay after monclk t d(1) 5.0 10 15 ns monfrm delay after monclk t d(2) 5.0 10 15 ns monfrm pulse width t pw 500 648 ns monfrm period t fcyc 125 s mondto monclk (output) (output) t d(1) t pwl t pwh t cyc t d(2) monfrm (output) when control bit enmonfr=1 bit 192 bit 0 (frame bit) t fcyc t pw
- 35 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 12. receive highway timing - transmission mode (recovered receive line clock) notes: 1. transmission mode is selected when a low is placed on the config1 pin (pin 43). the recovered receive line clock (rclkn) and an internal sync pulse are used to clock out data (rdatan), signaling (rsigln), and the sync pulse (rsyncn) to the sys- tem, when control bits rxc and rse (bits 5 and 3 in register x02h) are 10 or 11. control bit rxc selects the clock source, whil e rse enables/disables the receive slip buffer. the position of rsyncn with respect to the rdatan/rsigln signals can be off- set. the values written to register 018h will determine the offset. rsyncn is shown for an offset value equal to zero. 2. usually, the minimum high time or low time has to be in the order of 290 ns for the part to be able to function over the enti re sysclk range of 16-22 mhz. however, if line clock high or low times fall to 240 ns, the device can only operate satisfactorily with the sysclk between 20-22 mhz. parameter symbol min typ max unit rclkn clock period t cyc 648 ns rclkn low time (see note 2) t pwl 240 324 408 ns rclkn high time (see note 2) t pwh 240 324 408 ns rdatan/rsigln delay after rclkn t d 0.0 5.0 10 ns rsyncn delay after rclkn t d(1) 0.0 5.0 10 ns rsyncn pulse width t pw 500 648 750 ns rsyncn period t fcyc 3.0 ms rclkn rdatan rsigln t d t cyc rsyncn bit 191 bit 192 t pwl bit 0 (frame bit) (output) (outputs) (output) t pwh t pw t d(1) note: n=1, 2, 3, 4 t fcyc
- 36 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 13. receive highway timing - transmission mode (system clock) notes: 1. the transmission mode is selected when a low is placed on the config1 pin (pin 43). the system clock (rclkn) and sync pulse (rsyncn) are used to clock data out of the slip buffer when control bits rxc and rse (bits 5 and 3 in register x02h) are 01. control bit rxc selects the clock source, while rse enables/disables the receive slip buffer. the position of rsyncn with respect to the rdatan/rsigln signals can be offset. the value written to register 018h compensates for any offset. rsyncn is shown for an offset equal to zero. 2. only one rising edge of rclkn may occur during the time interval (t pw ) of the positive pulse for the rsyncn input. 3. usually, the minimum high time or low time has to be in the order of 290 ns for the part to be able to function over the enti re sysclk range of 16-22 mhz. however, if line clock high or low times fall to 240 ns, the device can only operate satisfactorily with the sysclk between 20-22 mhz. parameter symbol min typ max unit rclkn clock period t cyc 648 ns rclkn low time (see note 3) t pwl 240 324 408 ns rclkn high time (see note 3) t pwh 240 324 408 ns rdatan/rsigln delay after rclkn t d 5.0 20 35 ns rsyncn setup time to rclkn t su 20 ns rsyncn hold time after rclkn t h 20 ns rsyncn period t fcyc 3.0 ms rsyncn pulse width (see note 2) t pw 1 x t cyc ns rclkn rdatan rsigln t cyc rsyncn t pwl (input) (outputs) (input) t pwh note: n=1, 2, 3, 4 t su t h t d bit 191 bit 192 bit 0 (frame bit) t fcyc t pw
- 37 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 14. transmit highway timing - transmission mode notes: 1. the transmission mode is selected when a low is placed on the config1 pin (pin 43). the position of tsyncn may be offset with respect to the tdatan/tsigln signals. the value written to register 017h compensates for any offset. tsyncn is shown for an offset equal to zero. 2. only one rising edge of tclkn may occur during the time interval (t pw ) of the positive pulse for the tsyncn input. 3. usually, the minimum high time or low time has to be in the order of 290 ns for the part to be able to function over the enti re sysclk range of 16-22 mhz. however, if line clock high or low times fall to 240 ns, the device can only operate satisfactorily with the sysclk between 20-22 mhz. parameter symbol min typ max unit tclkn clock period t cyc 648 ns tclkn low time (see note 3) t pwl 240 324 408 ns tclkn high time (see note 3) t pwh 240 324 408 ns tdatan/tsigln set-up time to tclkn t su(1) 20 ns tdatan/tsigln hold time after tclkn t h(1) 20 ns tsyncn set-up time to tclkn t su(2) 20 ns tsyncn hold time after tclkn t h(2) 20 ns tsyncn period t fcyc 3.0 ms tsyncn pulse width (see note 2) t pw 1 x t cyc ns tclkn tdatan tsigln t cyc tsyncn bit 191 bit 192 t pwl bit 0 (frame bit) (input) (inputs) (input) t pwh note: n=1, 2, 3, 4 t su(2) t h(2) t su(1) t h(1) t fcyc t pw
- 38 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 15. receive highway timing - mvip mode notes: 1. the mvip mode is selected when a high is placed on the config1 pin (pin 43). the receive slip buffer is always enabled in thi s mode. the position of rsyncn may be offset with respect to the rdatan/rsigln signals. the value written to register 018h compensates for any offset. rsyncn is shown for an offset equal to zero. 2. for bit number per mvip bit identification nomenclature, bit 256 is bit 0 of time slot 31, bit 1 is bit 7 of time slot 0 and bit 2 is bit 6 of time slot 0. parameter symbol min typ max unit rclkn clock period t cyc 465 488.3 513 ns rclkn low time t pwl 220 244 268 ns rclkn high time t pwh 220 244 268 ns rdatan/rsigln delay after rclkn t d 5.0 8.0 15 ns rsyncn set-up time to rclkn t su 10 ns rsyncn hold time after rclkn t h 5.0 ns rsyncn pulse width low time t pw 200 488 500 ns rsyncn period t fcyc 125 s rclkn rdatan rsigln t cyc rsyncn bit 256 bit 1 (first bit of time slot 0) t pwh t d t pwl t h t su t pw (input) (outputs) (input) note: n=1, 2, 3, 4 bit 2 (second bit of time slot 0) (see note 2) t fcyc
- 39 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 16. transmit highway timing - mvip mode notes: 1. the mvip mode is selected when a high is placed on the config1 pin (pin 43). the transmit slip buffer is always enabled in this mode. the position of tsyncn may be offset with respect to the tdatan/tsigln signals. the value written to register 017h compensates for any offset. tsyncn is shown for an offset equal to zero. 2. for bit number per mvip bit identification nomenclature, bit 256 is bit 0 of time slot 31, bit 1 is bit 7 of time slot 0 and bit 2 is bit 6 of time slot 0. parameter symbol min typ max unit tclkn clock period t cyc 480 488.3 497 ns tclkn low time t pwl 220 244 268 ns tclkn high time t pwh 220 244 268 ns tdatan/tsigln set-up time to tclkn t su(1) 10 ns tdatan/tsigln hold time after tclkn t h(1) 10 ns tsyncn set-up time to tclkn t su 5.0 ns tsyncn hold time after tclkn t h 5.0 ns tsyncn pulse width low time t pw 200 488 500 ns tsyncn period t fcyc 125 s tclkn tdatan tsigln t cyc tsyncn bit 256 bit 1 (first bit of time slot 0) t pwh t pwl t h t su t pw (input) (inputs) (input) note: n=1, 2, 3, 4 t su(1) t h(1) bit 2 (second bit of time slot 0) (see note 2) t fcyc
- 40 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 17. receive highway timing - fractional t1 gapped clock (transmission mode) notes 1. the fractional t1 gapped clock feature is enabled when the config1 pin is low and control bit ft1m (bit 0 in register x02h) i s written with a 1. one or more ds0 channels may be selected by writing a 1 to one or more control bits rfd1-rfd24 (in regis- ters x3ah-x3ch). 2. usually, the minimum high time or low time has to be in the order of 290 ns for the part to be able to function over the enti re sysclk range of 16-22 mhz. however, if line clock high or low times fall to 240 ns, the device can only operate satisfactorily with the sysclk between 20-22 mhz. parameter symbol min typ max unit rclkn clock period t cyc 648 ns rclkn low time (see note 2) t pwl 240 324 408 ns rclkn high time (see note 2) t pwh 240 324 408 ns rdatan delay after rclkn t d(1) 5.0 10 20 ns rft1gcn delay after rclkn t d(2) 12 20 25 ns rsyncn delay after rclkn t d(3) 5.0 10 20 ns rsyncn pulse width t pw 500 648 750 ns rclkn (output) rdatan (output) rft1gcn (output) rsyncn (output) f0123456789 t d(3) t pw t d(2) t pwl t pwh t cyc t d(1) ch1 when selected 192
- 41 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 18. transmit highway timing - fractional t1 gapped clock (transmission mode) notes 1. the fractional t1 gapped clock feature is enabled when the config1 pin is low (transmission mode) and control bit ft1m (bit 0 in register x02h) is written with a 1. one or more ds0 channels may be selected by writing a 1 to one or more control bits tfd1-tfd24 (in registers x3dh-x3fh). 2. usually, the minimum high time or low time has to be in the order of 290 ns for the part to be able to function over the enti re sysclk range of 16-22 mhz. however, if line clock high or low times fall to 240 ns, the device can only operate satisfactorily with the sysclk between 20-22 mhz. parameter symbol min typ max unit tclkn clock period t cyc 648 ns tclkn low time (see note 2) t pwl 240 324 408 ns tclkn high time (see note 2) t pwh 240 324 408 ns tdatan set-up time to tclkn t su(1) 20 ns tdatan hold time after tclkn t h(1) 20 ns tsyncn set-up time to tclkn t su(2) 20 ns tsyncn hold time after tclkn t h(2) 20 ns tft1gcn output delay from tclkn t d 5.0 10 15 ns f0123456789 t pwl t pwh t cyc t su(1) for the ds0 channel selected t d tclkn (input) tdatan (input) tft1gcn (output) tsyncn (input) t h(1) t h(2) t su(2) 192
- 42 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 19. shadow register timing note: the shadow register feature and this input are enabled when a 1 is written to control bit enpmfm (bit 3 in register 006h). parameter symbol min typ max unit t1si clock period t cyc 1.0 sec t1si pulse width high t pwh 0.50 50 100 ms t1si pulse width low t pwl 6.0 950 980 ms t1si (input) t pwl t pwh t cyc
- 43 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 20. boundary scan timing parameter symbol min max unit tck clock high time t pwh 50 ns tck clock low time t pwl 50 ns tms setup time to tck t su(1) 3.0 - ns tms hold time after tck t h(1) 2.0 - ns tdi setup time to tck t su(2) 5.0 - ns tdi hold time after tck t h(2) 5.0 - ns tdo delay from tck t d 2.0 10 ns tms tdi tdo t d tck (input) (input) (input) (output) t h(2) t su(2) t su(1) t h(1) t pwh t pwl
- 44 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 21. intel microprocessor read cycle timing notes: 1. the intel microprocessor bus is selected by placing a low on the moto pin (pin 99). 2. the system clock has a nominal frequency of 16-19 mhz (22 mhz max for v dd = +5.0 volts). 3. both sel and rd must be simultaneously low for the specified t pw(1) interval. 4. as indicated in the waveform diagram, a brief excursion to the high state, of 2 or 3 ns duration, may occur when the rdy output leaves the tristate condition to go low. parameter symbol min typ max unit addr(11-0) valid setup time to sel t su(1) 10 ns addr(11-0) hold time after s el t h(1) 0.0 ns dat(7-0) valid delay after rdy t d(1) -1/2 cycle of sysclk -10 ns dat(7-0) float time after rd t f 4.0 10 15 ns sel hold time after rd t h(2) 5.0 ns rd pulse width low time (note 3) t pw(1) 25 ns rdy pulse width low time t pw(2) 2 cycles of sysclk 10 cycles of sysclk 15 cycles of sysclk ns rdy tristate to low delay after the latter of sel or rd (see note 4) t d(3) 5.0 7.0 20 ns rdy high to tristate delay after sel t d(4) 5.0 ns addr(11-0) dat(7-0) sel rd rdy t h(2) t f t d(1) t pw(2) t su(1) t pw(1) (input) (output) (input) (input) (output) tristate tristate t d(4) t d(3) t h(1)
- 45 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 22. intel microprocessor write cycle timing notes: 1. the intel microprocessor bus is selected by placing a low on the moto pin (pin 99). 2. the system clock has a nominal frequency of 16-19 mhz (22 mhz max for v dd = +5.0 volts). 3. * wait states only occur if a write cycle immediately follows a previous read/write cycle (e.g., read, modify, write or word-wide write). 4. the timing is with respect to the earlier of the two rising edges. 5. as long as both sel and wr are simultaneously low for the specified t pw(1) interval, sel may rise prior to wr ( t h(3) is a negative min). 6. when writing to address x0ah (hdlc transmit fifo) only, allow a minimum of 2 cycles of sysclk between rdy and sel or wr . parameter symbol min typ max unit addr(11-0) valid setup time to sel t su(1) 5.0 ns addr(11-0) hold time after wr , sel (note 4) t h(1) 10 ns dat(7-0) valid setup time to wr , sel (note 4) t su(2) 10 ns dat(7-0) hold time after wr , sel (note 4) t h(2) 10 ns sel hold time after wr (note 5) t h(3) 0.5 ns wr pulse width low time/sel pulse width low time (note 5) t pw(1) 50 ns rdy delay after wr t d(2) 4.0 7.0 15 ns rdy pulse width low time t pw(2) 0.0 7 cycles of sysclk* 10 cycles of sysclk* ns rdy tristate to high delay after the latter of sel or wr t d(3) 5.0 7.0 15 ns rdy high to tristate delay after sel t d(4) 5.0 7.0 15 ns wr and sel hold time after rdy goes high (note 4) t h(5) 0.0 ns rdy to wr , or sel (note 6) t h(4) 2 cycles of sysclk ns addr(11-0) dat(7-0) sel wr rdy t h(2) t su(1) t pw(2) t d(2) t pw(1) t su(2) t h(1) (input) (input) (input) (input) (output) tristate tristate t d(4) t d(3) t h(5) t h(3) t h(4)
- 46 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 23. motorola microprocessor read cycle timing notes: 1. the motorola microprocessor bus is selected by placing a high on the moto pin (pin 99). 2. the system clock has a nominal frequency of 16-19 mhz (22 mhz max for v dd = +5.0 volts). parameter symbol min typ max unit addr(11-0) valid setup time to sel t su(1) 10 ns addr(11-0) hold time after sel t h(1) 0.0 ns dat(7-0) delay to tristate after sel t d(3) 3.0 ns dat(7-0) valid output delay after dtack t d(1) -1 cycle of sysclk -1/2 cycle of sysclk -10 ns sel pulse width low time t pw(1) 50 ns rd/wr setup time to sel t su(3) 10 ns rd/w r hold time after s el t h(2) 5.0 ns dtack pulse width high time t pw(2) 2 cycles of sysclk 10 cycles of sysclk 15 cycles of sysclk ns dtack float time after sel t f 5.0 8.0 15 ns dtack delay after sel t d(2) 3.0 8.0 12 ns addr(11-0) dat(7-0) sel rd/wr dtack t f t d(3) t d(1) t pw(2) t su(3) t su(1) t pw(1) t d(2) (input) (output) (input) (input) (output) tristate tristate t h(2) t h(1)
- 47 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 24. motorola microprocessor write cycle timing notes: 1. the motorola microprocessor bus is selected by placing a high on the moto pin (pin 99). 2. the system clock has a nominal frequency of 16-19 mhz (22 mhz max for v dd = +5.0 volts). 3. * wait states only occur if a write cycle immediately follows a previous read or write cycle (e.g., read, modify, write or word-wide write). 4. sel and rd/wr must both be low simultaneously for the specified t pw(1) period. 5. when writing to address x0ah (hdlc transmit fifo) only, allow a minimum of 2 cycles of sysclk between dtack and sel or rd/wr . parameter symbol min typ max unit addr(11-0) valid setup time to sel t su(1) 10 ns addr(11-0) hold time after sel t h(1) 10 ns dat(7-0) valid setup time to sel t su(2) 15 ns dat(7-0) hold time after sel t h(2) 10 ns sel pulse width low time (note 4) t pw(1) 50 ns rd/wr setup time to sel t su(3) 10 ns rd/wr hold time after sel t h(3) 10 ns dtack pulse width high time t pw(2) 0.0 10 cycles of sysclk* 15 cycles of sysclk* ns dtack float time after sel t f 3.0 7.0 12 ns dtack delay after sel t d(2) 3.0 7.0 12 ns sel hold time after dtack t h(5) 0.0 ns dtack to sel or rd/ wr (note 5) t h(4) 2 cycles of sysclk ns addr(11-0) dat(7-0) sel rd/wr t f t pw(2) t su(1) t su(3) dtack t su(2) t h(2) t pw(1) t d(2) t h(1) (input) (input) (input) (input) (output) tristate tristate t h(3) t h(5) t h(4)
- 48 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 25. clock reference timing notes: 1. clkref1 and clkref2 output pins are controlled by register 019h. control bit 1544khz selects either a direct clock output when set to 1 or via a divide by 193 circuit when set to 0. control bits enref1 and enref2 enables output pins clkref1 and clkref2 when set to 1; when enref1 and enref2 are set to 0 clkref1 and clkref2 are tristated. the particular receive clock lrclkn used as a reference is selected by control bits cr1s1,2 for clkref1 and control bits cr2s1,2 for clkref2. 2. the actual clock period and high or low times are a function of the selected clock lrclkn. 3. a fault detected (los or lint pin active if enabled by control bit lie) by the particular channel selected for the refer- ence clock will cause clkref1,2 to stay low. the output only goes to tristate if control bit enref1 or enref2 is set to 0. parameter symbol min typ max unit clkref1,2 clock period when control bit 1544khz = 1; see note 2 t cyc(1) 648 ns clkref1,2 high time when control bit 1544khz = 1; see note 2 t pwh(1) 324 ns clkref1,2 low time when control bit 1544khz = 1; see note 2 t pwl(1) 324 ns clkref1,2 clock period when control bit 1544khz = 0; see note 2 t cyc(2) 125 ms clkref1,2 high time when control bit 1544khz = 0; see note 2 t pwh(2) 560 648 ns clkref2 (output) t pwl(1) t pwh(1) t cyc(1) clkref2 (output) t cyc(2) t pwh(2) (control bit 1544khz = 1) (control bit 1544khz = 0) clkref1 clkref1 note 3 note 3
- 49 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers operation the following sections detail the internal operation of the qt1f- plus . line interface selection each of the four framers in the qt1f- plus can be programmed to provide either a dual unipolar interface or a nrz inter- face. the dual unipolar interface is selected when a 1 is written into control bit rail (bit 7) in the framer configuration reg - ister located at address x00h in the memory map. the x stands for the framer selected, and will be equal to the value n used to identify the framer (1 for framer 1, 2 for framer 2, etc.). the b8zs line or ami coder/decoder (codec) feature can be selected for the dual unipolar interface. the b8zs codec is selected by writing a 1 to control bit be (bit 6) in the framer configuration register x00h. a 0 will select an ami codec. the b8zs stands for bipolar with eight zero substi- tution, which is described in ansi document ansi t1.102-1993 and other bellcore documents. the clock polarity of the input and output line clocks is selectable by writing the sense required to control bits txcp and rxcp (bits 7 and 6) in the framer configuration register x01h. when a framer is configured for the dual unipolar mode, the line signal is monitored for loss of signal (los). los is detected if no transitions are present for 175 75 pulse posi- tions. recovery occurs when a ones density of 12.5% or more is detected in 175 75 pulse positions. the connections between a qt1f- plus framer and external line interface transceivers are shown in figure 26 below for dual unipolar mode. figure 26. line interface for dual unipolar mode line interface transceiver qt1f- plus receive rposn rnegn lrclkn tposn tnegn lt c l k n lcsn lintn lsclk lsdo lsdi cs los sclk sdi sdo rxtip rxring txtip txring transmit note: n is the channel number (1, 2, 3, 4) other tr a n s c e i v e r s for channel n
- 50 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers the nrz interface is selected when a 0 is written into control bit rail (bit 7) in register x00h. the clock polarity of the lin e input and output clocks is selectable by writing to control bits txcp and rxcp (bits 7 and 6) in the framer configuration register x01h. options are provided for inverting the polarity of the transmit and receive data pins. a 1 written to control bi t txnrzp (bit 5) in register x01h inverts the polarity of the transmit data signal, tldatn, while a 1 written to control bit rxnrzp (bit 0) in the same register inverts the polarity of the receive data signal rldatn. in nrz mode, the rnegn pin may be used to input an external indication of coding violations (rlbpvn) or a fast sync pulse for testing purposes (rfsn). external coding violations are counted in a 16-bit performance counter when control bit rxfs (bit 1) in register x06h is a 0. coding violations are counted when the input is high for rising edges of the line clock lrclkn. when control bit rxfs is a 1, this pin is used for inputting a receive fast sync pulse. in the transmit direction, when the nrz mode is selected, the tnegn pin becomes a tfsn or tmoden pin. the pin may be used to output a fast sync pulse (tfsn), or it may be used as a general purpose output pin (tmoden). when control bit txfs (bit 0) in register x06h is a 1, a fast sync output pulse is provided on this pin. when control bit txfs is a 0, this pin can be used as a general purpose output pin. the output state is defined by the value written to bit be (bit 6) in register x00h. a typical interface between a framer in the qt1f- plus and an external line transceiver is shown in figure 27 below for the nrz mode. figure 27. line interface for nrz mode qt1f- plus receive rldatn rlbpvn lrclkn tldatn tmoden lt c l k n lcsn lintn lsclk lsdo lsdi cs los sclk sdi sdo rxtip rxring txtip txring transmit note: n is the channel number (1, 2, 3, 4) other transceivers line interface tr a n s c e i v e r for channel n
- 51 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers line interface control this interface permits the microprocessor to have complete control of the four external line interface transceivers through the qt1f- plus . this interface is selected by placing a low on the config2 pin (pin 42). the line interface control leads are common to all four framers and comprise a data input pin (lsdi), a data output pin (lsdo), and a clock output pin (lsclk). the clock signal lsclk is derived from the signal at the lo pin (pin 41) and has the same clock period. individ- ual chip select pins (lcsn ) are used between the qt1f- plus and the external transceivers to determine which of the four external transceivers is to be accessed through the qt1f- plus . in addition, general purpose input leads (lintn) are pro- vided. the signal on this lead is locally or-gated with the internal loss of signal alarm when control bit lie (bit 1) in the framer configuration register x00h is a 1. the operating sense of this lead is programmable by control bit lpol (bit 0) in the framer configuration register x00h. the status indication of this pin is given by the lint status bit (bit 0) in register x15h. typical interfaces between the qt1f- plus and external line interface transceivers using the line interface control pins are shown in figures 26 and 27 , for the dual unipolar and nrz interface modes, respectively. data to be written to the external transceiver is formatted as a two-byte message. the first byte is an address/command byte and the second byte contains the data to be written or read. figure 28 illustrates the message and control formats associated with the transceiver serial input/output timing. figure 28. transceiver serial input/output timing the format of the address/command byte depends upon the external transceiver being controlled. please refer to the transceiver's data sheet for the command/data formats. the interface for controlling the external transceiver operates in the following way. the external transceiver selection (via lcsn ) is determined by the value written to two t1chcs bits (bits 1 and 0) in register 013h. for example, a 00 value selects the transceiver for framer 1 while a 11 value selects the transceiver for framer 4. the microprocessor writes the command byte to lcb7-lcb0 in the line interface control regis- ter 010h. this is followed by writing the data byte to ldo7-ldo0 in line interface control register 011h. the serial mes- sage is sent on lsdo when a 1 is written to replace the 0 in the esp/emon bit (bit 4) in register 013h. the esp/emon bit must be first written with a 0, followed by a 1, before another transfer can take place between the qt1f- plus and the external transceiver selected. broadcast capability to all transceivers is enabled when the control bit bdcst (bit 7) in reg- ister 013h is written with a 1. eight clock cycles later, the selected transceiver will respond by sending serial data on the lsdi input pin. the data is shifted in lsb first to ldi7-ldi0 in the serial port data input register 012h. lcsn lsclk lsdo lsdi addrd0d1d2d3d4d5 d6 d7 r/w addr addr addr addr addr addr data input/output address/command byte d0 d1 d2 d3 d4 d5 d6 d7
- 52 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers monitor mode the monitor mode interface permits the qt1f- plus to provide an external receive or transmit nrz signal from one of the framers to an external device. this interface is selected by placing a high on the config2 pin (pin 42). please note that the pins for this mode are shared with the line control interface, and if the monitor mode is selected, these pins cannot be used to provide a serial interface between the external transceivers and the qt1f- plus . in addition, a 1 must be written into the esp/emon control bit (bit 4) in the global configuration register 013h to enable the monitor mode interface out- put pins. a 0 written into this control bit causes these data and clock pins to be tristated, permitting multiple qt1f- plus devices to share an external device. a 1 written to control bit rxtx (bit 3) in register 013h selects the receive side, while a 0 selects the transmit side. the framer to be monitored is selected by the value written into the two t1chcs bits (bits 1 and 0) in register 013h. for exam- ple, a value of 00 selects framer 1, and a value of 11 selects framer 4. the selected framer nrz signal is provided on out- put pin mondto (pin 60). the nrz receive or transmit data is clocked out on rising edges of the clock monclk (pin 61). system interface the system interface connects each of the four framers within the qt1f- plus to and from the system. the system inter- face is selected by the config1 input pin, according to the table given below. for the transmission and mvip modes, each framer has separate transmit and receive interfaces that are referred to as receive and transmit highways. each highway consists of a data bus (i.e., data highway) rdatan/tdatan, a signaling bus (i.e., signaling highway) rsigln/tsigln, a clock rclkn/tclkn, and a synchronization signal rsyncn/tsyncn. internally, each data bus is connected to a two-frame slip buffer, and each signaling bus is connected to a 96-bit signaling buffer. please note that control bits are provided which enable the slip buffers to be bypassed when the transmission mode is selected. for the mvip mode, the receive and transmit slip buffers must be enabled by setting control bits rse (bit 3), and tse (bit 4) in register x02h to a 1. please note also that in the transmission mode, with the slip buffers bypassed, and the signaling disabled, signaling information contained in the data stream is passed through transparently . config1 pin 43 system interface low transmission mode. data highway, signaling highway, 1.544 mhz clock and 3 ms sync pulse for each framer in both transmit and receive directions. sync pulse is positive, and one clock cycle wide. the system receive clock and sync pulse may be outputs when slip buffer is bypassed. high mvip mode: data highway, signaling highway, 2.048 mhz clock, and 125 microsecond sync pulse for each framer in both transmit and receive directions. the slip buffers must be enabled. the system receive and transmit clock and sync pulses are inputs to the qt1f- plus . the negative sync pulses are one clock cycle wide.
- 53 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers transmission mode the transmission mode is enabled when a low is placed on the config1 pin (pin 43). transmit highway when the transmission mode is selected, the transmit highway carries information from the system to the qt1f- plus for each framer. the highway is subdivided into two time division multiplexed buses, one for data (tdatan), and the other one for signaling and alarms (tsigln). the n in the tdatan and tsigln signals represents one of the four framers. the two buses are synchronous with respect to the highway clock (tclkn), which has a clock rate of 1544 khz. the data highway is a single bit-serial bus organized into 193-bit groups called frames, with the bits in each group numbered 0 through 192. each frame consists of 24 ds0 channels, numbered from 1 to 24, as shown in figure 29 . bit 0 carries the frame synchronization bit and multiframe bit for the sf frame format, and synchronization bits. also note that 24 frames form a multiframe, with the beginning of each multiframe identified by an active high synchronization pulse (tsyncn), one (tclkn) clock cycle wide, which occurs every 3 ms, normally at the end of frame 24. each multiframe carries one extended superframe (esf) or two regular superframes (sf). the position of the tsyncn pulse is programmable to any bit position within the data bus frame using control bits tsd7-tsd0 in register 017h. the synchronization pulse is aligned to bit 8 in ds0 channel 24 in frame 24 when a value of 00h is written into this register. the signaling bus (tsigln) is also divided into 193-bit frames. each signaling frame consists of 193 bits of signaling and alarm information for the 24 ds0 channels, numbered from 1 to 24, that are carried on the data bus. the first bit in the signaling highway is assigned to carry the framing bits for the sf and esf frame formats. the transmit section of the framer will rewrite the ft and fs for the sf frame format. the framer will rewrite the ft bits, and recalculate the crc for the esf frame format. the hdlc link d bits (m-bits) may be inserted from the signaling highway. the sync pulse (tsync) determines the start of the frame and the first frame in the multiframe. the s1, s2, s3 and s4 bits represent the abcd signaling states associated with each of the ds0 channels. for example, if 16-state signaling is selected, frame 1 will carry the a1, a2, a3 and a4 signaling states in the s1, s2, s3 and s4 bits for ds0 channels 1, 2, 3 and 4. frame 2 in the multiframe will carry the a5, a6, a7 and a8 signaling states in the s1, s2, s3 and s4 bits for ds0 channels 5, 6, 7 and 8, while frame 24 in the multiframe will carry the d21, d22, d23 and d24 signal- ing states in the s1, s2, s3 and s4 bits for ds0 channels 21, 22, 23 and 24. the qt1f- plus inserts the signaling bits from the signaling highway into the robbed bit positions if enabled by control bits se1 through se24 in registers xe8, xe9, and xea. the next bit is defined as the y bit and defines the system remote defect indication alarm (yellow) alarm. the next 11 bits are not used. the bits in channels 3 through 24 carry a system ais alarm indication (a). status bits vtais (bit 3) and vtrdi (bit 2) in register x14h provide the active states of the ais bits and a remote defect indication on the signaling highway in the transmission mode. these vt alarms correspond to alarms that are present for a system sonet byte synchronous interface.
- 54 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 29. transmit highway - transmission mode tsyncn tclkn tdatan tsigln ch 24 8 bits per channel ch 3 ch 2 ch 1 aa a aaaaa a aa aa aaaa a aaaa aa frame 24 frame 3 frame 2 frame 1 one frame (193 bits) f s 125 s 3 ms (multiframe) -- -- - --- 2 s 1 s 3 s 4 y- - frame sf/esf 16-st. tsigl; s 1 -s 4 tsigl; s 1 -s 4 4-state; s 1 -s 4 2-state; s 1 -s 4 1 ft/di a01, a02, a03, a04 a01, a02, a03, a04 a01, a02, a03, a04 a01, a02, a03, a04 2 fs/crc a05, a06, a07, a08 a05, a06, a07, a08 a05, a06, a07, a08 a05, a06, a07, a08 3 ft/di a09, a10, a11, a12 a09, a10, a11, a12 a09, a10, a11, a12 a09, a10, a11, a12 4 fs/ft a13, a14, a15, a16 a13, a14, a15, a16 a13, a14, a15, a16 a13, a14, a15, a16 5 ft/di a17, a18, a19, a20 a17, a18, a19, a20 a17, a18, a19, a20 a17, a18, a19, a20 6 fs/crc a21, a22, a23, a24 a21, a22, a23, a24 a21, a22, a23, a24 a21, a22, a23, a24 7 ft/di b01, b02, b03, b04 b01, b02, b03, b04 b01, b02, b03, b04 a01, a02, a03, a04 8 fs/ft b05, b06, b07, b08 b05, b06, b07, b08 b05, b06, b07, b08 a05, a06, a07, a08 9 ft/di b09, b10, b11, b12 b09, b10, b11, b12 b09, b10, b11, b12 a09, a10, a11, a12 10 fs/crc b13, b14, b15, b16 b13, b14, b15, b16 b13, b14, b15, b16 a13, a14, a15, a16 11 ft/di b17, b18, b19, b20 b17, b18, b19, b20 b17, b18, b19, b20 a17, a18, a19, a20 12 fs/ft b21, b22, b23, b24 b21, b22, b23, b24 b21, b22, b23, b24 a21, a22, a23, a24 13 ft/di c01, c02, c03, c04 c01, c02, c03, c04 a01, a02, a03, a04 a01, a02, a03, a04 14 fs/crc c05, c06, c07, c08 c05, c06, c07, c08 a05, a06, a07, a08 a05, a06, a07, a08 15 ft/di c09, c10, c11, c12 c09, c10, c11, c12 a09, a10, a11, a12 a09, a10, a11, a12 16 fs/ft c13, c14, c15, c16 c13, c14, c15, c16 a13, a14, a15, a16 a13, a14, a15, a16 17 ft/di c17, c18, c19, c20 c17, c18, c19, c20 a17, a18, a19, a20 a17, a18, a19, a20 18 fs/crc c21, c22, c23, c24 c21, c22, c23, c24 a21, a22, a23, a24 a21, a22, a23, a24 19 ft/di d01, d02, d03, d04 d01, d02, d03, d04 b01, b02, b03, b04 a01, a02, a03, a04 20 fs/ft d05, d06, d07, d08 d05, d06, d07, d08 b05, b06, b07, b08 a05, a06, a07, a08 21 ft/di d09, d10, d11, d12 d09, d10, d11, d12 b09, b10, b11, b12 a09, a10, a11, a12 22 fs/crc d13, d14, d15, d16 d13, d14, d15, d16 b13, b14, b15, b16 a13, a14, a15, a16 23 ft/di d17, d18, d19, d20 d17, d18, d19, d20 b17, b18, b19, b20 a17, a18, a19, a20 24 fs/ft d21, d22, d23, d24 d21, d22, d23, d24 b21, b22, b23, b24 a21, a22, a23, a24 notes: an, bn, cn, dn = signaling states where n is the ds0 channel number y = remote defect indication (yellow) alarm f = frame synchronization bit (sf/esf) - framing bit
- 55 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers receive highway in the transmission mode, the receive highway for each framer carries information from the qt1f- plus to the system. like the transmit path, the receive highway is also subdivided into two time division multiplexed buses, one for data (rdatan), and one for signaling and alarms (rsigln), where n represents one of the four framers. the two buses are synchronous with the highway clock (rclkn), which has a clock rate of 1544 khz. the clock (rclkn) is either an output to the system or an input from the system. the system clock (rclkn) or the line clock (lrclkn) may be the input clock source for the slip buffer when it is enabled. usually the system clock (rclkn) is used. the qt1f- plus sources the clock (rclkn) as an output when the slip buffer is bypassed. the receive slip buffer for a framer is disabled when a 0 is written to the rse bit (bit 3) in the framer configuration register x02h. the clock source selection is determined by the rxc bit (bit 5) in register x02h. a 0 written into this bit position selects the system clock (rclkn) as the source clock. in addition to controlling the source of the clock, control bit rxc also controls the source of the sync pulse. the data bus is a single bit-serial bus organized into 193-bit groups called frames, as shown in figure 30 . each frame consists of 24 time slots, plus a frame synchronization bit, as shown for the transmit interface. twenty-four frames form a multiframe, with the beginning of each multiframe identified by an active high synchronization pulse (rsyncn), one (rclkn) clock cycle wide, which occurs every 3 ms, normally at the end of frame 24. each multiframe carries one extended superframe (esf) or two regular superframes (sf). the position of the rsyncn pulse is programmable to any bit position within the frame using control bits rsd7-rsd0 in register 018h. the synchronization pulse is aligned to bit 8 in ds0 channel 24 in frame 24 when a value of 00h is written into this register. the signaling bus (rsigln) is also divided into 193-bit frames. each signaling frame consists of 193 bits of signaling and alarm information for the 24 data channels carried on the data bus. the first bit in the signaling highway carries the fram- ing bits for the sf and esf frame formats which are the line framing bits. the s1, s2, s3 and s4 bits represent the abcd signaling states associated with each of the ds0 channels. for example, if 16-state signaling is selected, frame 1 will carry the a1, a2, a3 and a4 signaling states in the s1, s2, s3, and s4 bits for ds0 channels 1, 2, 3 and 4. frame 2 in the multiframe will carry the a5, a6, a7 and a8 signaling states in the s1, s2, s3 and s4 bits for ds0 channels 5, 6, 7 and 8, while frame 24 in the multiframe will carry the d21, d22, d23 and d24 signaling states in the s1, s2, s3 and s4 bits for ds0 channels 21, 22, 23 and 24. the next bit is defined as the y bit and provides the system with the line yellow alarm status. the next 11 bits are not used. the bits in channels 3 through 24 carry an ais alarm indication (a). control bits enais, enoof, and enlos (bits 2, 1, and 0 of register x03h), when set to 1, enable the a bits to be set to a 1 if ais, oof, or los is detected.
- 56 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 30. receive highway - transmission mode rsyncn rclkn rdatan rsigln ch 24 8 bits per channel ch 3 ch 2 aa a aaaaa a aa aa aaaa a aaaa aa frame 24 frame 3 frame 2 frame 1 one frame (193 bits) 125 s 3 ms (multiframe) -- -- - --- frame sf/esf 16-st. rsigl; s 1 -s 4 rsigl; s 1 -s 4 4-state; s 1 -s 4 2-state; s 1 -s 4 1 ft/di a01, a02, a03, a04 a01, a02, a03, a04 a01, a02, a03, a04 a01, a02, a03, a04 2 fs/crc a05, a06, a07, a08 a05, a06, a07, a08 a05, a06, a07, a08 a05, a06, a07, a08 3 ft/di a09, a10, a11, a12 a09, a10, a11, a12 a09, a10, a11, a12 a09, a10, a11, a12 4 fs/ft a13, a14, a15, a16 a13, a14, a15, a16 a13, a14, a15, a16 a13, a14, a15, a16 5 ft/di a17, a18, a19, a20 a17, a18, a19, a20 a17, a18, a19, a20 a17, a18, a19, a20 6 fs/crc a21, a22, a23, a24 a21, a22, a23, a24 a21, a22, a23, a24 a21, a22, a23, a24 7 ft/di b01, b02, b03, b04 b01, b02, b03, b04 b01, b02, b03, b04 a01, a02, a03, a04 8 fs/ft b05, b06, b07, b08 b05, b06, b07, b08 b05, b06, b07, b08 a05, a06, a07, a08 9 ft/di b09, b10, b11, b12 b09, b10, b11, b12 b09, b10, b11, b12 a09, a10, a11, a12 10 fs/crc b13, b14, b15, b16 b13, b14, b15, b16 b13, b14, b15, b16 a13, a14, a15, a16 11 ft/di b17, b18, b19, b20 b17, b18, b19, b20 b17, b18, b19, b20 a17, a18, a19, a20 12 fs/ft b21, b22, b23, b24 b21, b22, b23, b24 b21, b22, b23, b24 a21, a22, a23, a24 13 ft/di c01, c02, c03, c04 c01, c02, c03, c04 a01, a02, a03, a04 a01, a02, a03, a04 14 fs/crc c05, c06, c07, c08 c05, c06, c07, c08 a05, a06, a07, a08 a05, a06, a07, a08 15 ft/di c09, c10, c11, c12 c09, c10, c11, c12 a09, a10, a11, a12 a09, a10, a11, a12 16 fs/ft c13, c14, c15, c16 c13, c14, c15, c16 a13, a14, a15, a16 a13, a14, a15, a16 17 ft/di c17, c18, c19, c20 c17, c18, c19, c20 a17, a18, a19, a20 a17, a18, a19, a20 18 fs/crc c21, c22, c23, c24 c21, c22, c23, c24 a21, a22, a23, a24 a21, a22, a23, a24 19 ft/di d01, d02, d03, d04 d01, d02, d03, d04 b01, b02, b03, b04 a01, a02, a03, a04 20 fs/ft d05, d06, d07, d08 d05, d06, d07, d08 b05, b06, b07, b08 a05, a06, a07, a08 21 ft/di d09, d10, d11, d12 d09, d10, d11, d12 b09, b10, b11, b12 a09, a10, a11, a12 22 fs/crc d13, d14, d15, d16 d13, d14, d15, d16 b13, b14, b15, b16 a13, a14, a15, a16 23 ft/di d17, d18, d19, d20 d17, d18, d19, d20 b17, b18, b19, b20 a17, a18, a19, a20 24 fs/ft d21, d22, d23, d24 d21, d22, d23, d24 b21, b22, b23, b24 a21, a22, a23, a24 notes: an, bn, cn, dn = signaling states where n is the ds0 channel number y = remote defect indication (yellow) alarm f = frame synchronization bit (sf/esf) ch 1 framing bit f s 2 s 1 s 3 s 4 y- - -
- 57 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers mvip mode the mvip mode is enabled when a high is placed on the config1 pin (pin 43). transmit highway in the mvip mode, the transmit highway for each framer in the qt1f- plus carries input information from the system. the highway for framer n is subdivided into two time division multiplexed buses, one for data (tdatan), and one for signaling (tsigln). the two buses are synchronous with the highway clock (tclkn), which has a clock rate of 2048 khz. the data bus is a single bit-serial bus organized into 256-bit groups called frames. each frame consists of thirty-two time slots, 24 of which carry the 24 ds0 channels, as shown in the table below and in figure 31 . the frame start is identified by a synchronization pulse (tsyncn), which is one (tclkn) clock cycle wide and occurs every 125 microseconds. the position of the tsyncn pulse is programmable to any bit position within the frame using control bits tsd7-tsd0 in register 017h. the synchronization pulse is aligned to bit 1 in time slot 0 when a value of 00h is written into this register. the signaling bus (tsigln) is also divided into 256-bit frames. each signaling frame consists of 32 time slots, of which 24 time slots carry the abcd signaling bits associated with the 24 ds0 channels. like the data highway, time slots 0, 4, 8, 12, 16, 20, 24 and 28 do not carry signaling information. the signaling information (abcd) is carried in the last four bits of a signaling bus time slot. the first four bits in each signaling bus time slot should be set to zero. the signaling buffer is updated every other frame. the line signaling states are updated once every six frames. for 2 or 4- state signaling, the signaling buffer uses only the a or ab values to update the signaling buffer the control bit bfdl (bit 1 of register x01h), when set to a 1, will cause the transfer of the m-bits (fdl chan- nel) from the transmit signaling highway (tsigln) instead of generating them internally for the esf mode of operation. in sf mode, the fs bit is taken from the transmit signaling highway (tsigln) instead of being gener- ated internally. since the m-bits or the fs bits are taken every other frame, and since no multiframe indication is provided in mvip mode, each bit to be bypassed must be present for two frames on tsigln. changes in the slip buffer have no effect on this function. the purpose is to permit an alternative way of generating the fdl channel. figure 31 details the placement of the m-bit or fs bit. please note that, in mvip mode, none of the data highway clocks (rclkn, tclkn or the lo clock) should be shut off when the slip buffer is enabled. this could result in constant slip even after the clock(s) are restored. tdatan time slot 012345678910111213141516171819202122232425262728293031 ds1 ds0 no. x 1 2 3 x 4 5 6 x 7 8 9 x 10 11 12 x 13 14 15 x 16 17 18 x 19 20 21 x 22 23 24
- 58 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 31. transmit highway - mvip mode receive highway in the mvip mode, the receive highway for each framer carries output information from the qt1f- plus to the system. the highway for framer n is subdivided into two time division multiplexed buses, one for data (rdatan), and one for signaling (rsigln). the two buses are synchronous with the highway clock (rclkn), which has a clock rate of 2048 khz. the data bus is a single bit-serial bus organized into 256-bit groups called frames. each frame consists of thirty-two time slots, 24 of which carry the 24 ds0 channels, as shown in the table below and in figure 32 . the frame start is identified by a synchronization pulse (rsyncn), which is one (rclkn) clock cycle wide and occurs every 125 microseconds. the position of the rsyncn pulse is programmable by setting the values of the control bits rsd7-rsd0 in register 018h. the effect is always to restart the data and signaling highways during transmit or receive highway channel number 0. this time slot can become 9, 10, 11 or 12 bits long. since the frame does not provide any information in time slot 0 there is no effect on framer performance. the synchronization pulse is aligned to bit 1 in time slot 0 when a value of 00h is written into this register. the frame bits are presented on the receive signaling highway (rsigln) as they are received (not delayed or altered as a result of slip buffer slips). the purpose is to allow the fdl channel or frame bits to be accessed separately. the message bit (m-bit) is placed in bit 1 of time slot 1, representing the most recent value of the message bit (m-bit) 1 . to account for phase differences between the line and system frames, a small buffer of several bits is to be provided. figure 32 details the placement of the frame bit in the mvip mode. due to the lack of a multiframe indication in the mvip mode, and the difference in functionality between rsigln (all frame bits) and tsigln (fs or m-bits repeated), a loopback of rsigln to tsigln may not pass fs or m-bits properly . rdatan time slot 012345678910111213141516171819202122232425262728293031 ds1 ds0 no. x 1 2 3 x 4 5 6 x 7 8 9 x 10 11 12 x 13 14 15 x 16 17 18 x 19 20 21 x 22 23 24 1. note that m-bits correspond to f s bits in the sf mode. 125 s (frame) time slot 0 time slot 1 time slot 2 time slot 31 - - - - - - - - - - - mabcd - - - -abcd- - - -abcd- - - -abcd 8 bits per channel data bits for ch #1 data bits for ch #2 data bits for ch #24 abcd bits for ds0 ch #2 abcd bits for ds0 ch #24 tsyncn tclkn tdatan tsigln abcd bits for ds0 ch #1 notes: abcd = signaling bits for channel c (1-24). 18 18 18 18 18 time slots 0, 4, 8, 12, 16, 20, 24 and 28 do not carry signaling information and should be set to 0. time slot 1, bit 1, carriesthe m-bit (esf) or fs bit (sf) for optional bypass. each bit must be present for two consecutive frames.
- 59 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers the signaling bus (rsigln) is also divided into 256-bit frames. each signaling frame consists of 32 time slots, of which 24 time slots carry the abcd signaling bits associated with the 24 ds0 channels. like the data highway, time slots 0, 4, 8, 12, 16, 20, 24 and 28 do not carry signaling information and are set to zero, except for time slot 0, which carries eight ones. the signaling information (abcd) is carried in the last four bits of a signaling bus time slot. the first four bits in ea ch time slot are 0000. the signaling bus is updated from the signaling buffer every frame. the signaling buffer is updated by the line every six frames. for 2 or 4-state signaling, the bcd or cd values are identical to the a or ab values. for these repeated values the most recent a or ab bits are presented from the signaling buffer. figure 32. receive highway - mvip mode fractional t1 mode in the fractional t1 mode, the receive and transmit signaling (rsigln and tsigln) pins are reassigned to provide frac- tional t1 gapped clock signals rft1gcn and tft1gcn. the fractional t1 mode feature is only available in the trans- mission mode (i.e., when config1, pin 43, is low). the rsigln input lead becomes the rft1gcn (receive fractional t1 gapped clock) output lead and the tsigln input lead becomes the tft1gcn (transmit fractional t1 gapped clock) output lead. a gapped clock for a receive fractional t1 channel is enabled by writing a 1 to the ds0 channels required in control bits rfd1 to rfd24 (registers x3ah-x3ch). the fractional t1 gapped clock will have the same phase as the rclkn clock. a gapped clock for a transmit fractional t1 channel is enabled by writing a 1 to the ds0 channels required in control bits tfd1 to tfd24 (registers x3dh-x3fh). the fractional t1 gapped clock will have the same phase as the tclkn clock. the fractional t1 mode is enabled when the control bit ft1m (bit 0 in register x02h) is set to a one. 125 s (frame) time slot 0 time slot 1 time slot 2 time slot 31 1 1 1 1 1 1 1 1 0 0 0 mabcd 0 0 0 0abcd- 0 0 0abcd0 0 0 0abcd 8 bits per channel data bits for ch #1 data bits for ch #2 data bits for ch #24 abcd bits for ds0 ch #2 abcd bits for rsyncn rclkn rdatan rsigln abcd bits for ds0 ch #1 18 18 18 18 18 ds0 ch #24 notes: abcd = signaling bits for channel c (1-24). time slots 0, 4, 8, 12, 16, 20, 24 and 28 do not carry signaling information and are equal to 0, except for time slot 0, which carries eight ones. time slot 1, bit 1, carries the currently received m-bit.
- 60 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers per ds0 inversion mode the same control pins and bits involved in the fractional t1 mode, i.e., config1 (pin 43), ft1m (bit 0 in register x02h), rfdc (c=1-24, in registers x3ah-x3ch) and tfdc (c=1-24, in registers x3dh-x3fh), combine to give the per ds0 inversion mode, which operates in both transmission and mvip modes. with ft1m set to a zero, the bits rfdc, when set high, will invert the corresponding ds0 in rdatan on the receive data highway, (after the receive slip buffer) in either transmission mode or mvip mode, depending on the state of the config1 pin. similarly, with the ft1m bit set to a zero, the bits tfdc, when set high, will invert the corresponding ds0 in tdatan on the transmit data highway (before the data is clocked into the transmit slip buffer), in either transmission or mvip mode (depending on the state of config1). the corresponding data streams on the transmit/receive signaling highways are, however, not inverted. but, the corre- sponding signaling data bits (for the inverted ds0s) that are still carried in the rdatan/tdatan streams are inverted. please also note that in the mvip mode, time slots 4n (n=0-7) cannot be inverted, since they are not assigned to ds0s. the actions are summarized in the following table: framing frame structure each of the four framers can select either the d4 sf (superframe) or esf (extended superframe) frame format for oper- ations. the d4 sf frame format structure is shown in figure 33 . the sf format consists of 12 ds1 frames (or 2316 bits). each ds1 frame consists of 193 bit positions. the first bit, the f bit, carries the pattern for frame alignment (ft bits) and signaling phase alignment (fs bits). the other 192 bits in the frame are used to carry 24 ds0 channels (eight bits per channel). bit 2 in each ds0 channel is alternately assigned to carry a yellow alarm indication when set to zero. the japa- nese standard designates the fs bit in frame 12 of the 12 frame superframe, which is normally is a 0, as the yellow alarm indication. the yellow alarm indicates that the distant end has detected a loss of signal or frame. the sf format carries either 2-state signaling or 4-state signaling by using bit 8 in the ds0 channels in frames 6 and 12 of the 12-frame super- frame. ft1m bit 0 x02h config1 pin 43 system inter- face mode rsigln/ rft1gcn tsigln/ tft1gcn rfd1- rfd24 tfd1- tfd24 mode 0low 1.544 mbit/s transmission signaling out signaling in invert data on rdatan ds0 1-24 if set to a 1. invert data on tdatan ds0 1-24 if set to a 1. normal 1low 1.544 mbit/s transmission gapped clock out gapped clock out control rx gapped clock for ds0 1-24 if set to a 1. control tx gapped clock for ds0 1-24 if set to a 1. fractional t1 0high 2 mbit/s mvip signaling out signaling in invert data on rdatan ds0 1-24 if set to a 1. invert data on tdatan ds0 1-24 if set to a 1. normal 1high illegal control state - do not use
- 61 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 33. d4 sf framing structure frame # 1st bit in frame f-bit bit use for each time-slot signaling options fs ft data ya signaling none 2-state 4-state 1 0 - 1 bits 1-8 bit 2 none - - - 2 193 0 - bits 1-8 bit 2 none - - - 3 386 - 0 bits 1-8 bit 2 none - - - 4 579 0 - bits 1-8 bit 2 none - - - 5 772 - 1 bits 1-8 bit 2 none - - - 6 965 1 - bits 1-7 bit 2 bit 8 - a a 7 1158 - 0 bits 1-8 bit 2 none - - - 8 1351 1 - bits 1-8 bit 2 none - - - 9 1544 - 1 bits 1-8 bit 2 none - - - 10 1737 1 - bits 1-8 bit 2 none - - - 11 1930 - 0 bits 1-8 bit 2 none - - - 12 2123 0 or ya - bits 1-7 bit 2 bit 8 - a b
- 62 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers the esf frame format structure consists of 24 ds1 frames, as shown in figure 34 . each ds1 frame consists of 193 bit positions. the first bit, the f bit, carries the pattern for frame alignment (fps bits), a 4 kbit/s hdlc link (d bits), and a crc-6. the crc-6 is used for performance monitoring purposes. the other 192 bits in the frame are used to carry 24 ds0 channels (eight bits per channel). the yellow alarm is indicated by setting the hdlc link bits to a sequence of 8 ones followed by 8 zeros. the yellow alarm indicates that the distant end has detected a loss of signal or frame. the esf for- mat carries either 2, 4 or 16-state signaling by using bit 8 in the ds0 channels in frame 6, 12, 18 and 24. figure 34. esf framing structure frame # 1st bit in frame f-bit bit use for each time-slot robbed bit signaling options fps di crc data signaling none 2-state 4-state 16-state 1 0 -d-bits 1-8none---- 2 193 - 1bits 1-8none---- 3 386 -d-bits 1-8none---- 4 579 0 -bits 1-8none---- 5 772 -d-bits 1-8none---- 6 965 - 2 bits 1-7 bit 8 - a a a 7 1158 -d-bits 1-8none---- 8 1351 0 -bits 1-8none---- 9 1544 -d-bits 1-8none---- 10 1737 - 3bits 1-8none---- 11 1930 -d-bits 1-8none---- 12 2123 1 - bits 1-7 bit 8 - a b b 13 2316 -d-bits 1-8none---- 14 2509 - 4bits 1-8none---- 15 2702 -d-bits 1-8none---- 16 2895 0 -bits 1-8none---- 17 3088 -d-bits 1-8none---- 18 3281 - 5 bits 1-7 bit 8 - a a c 19 3474 -d-bits 1-8none---- 20 3667 1 -bits 1-8none---- 21 3860 -d-bits 1-8none---- 22 4053 - 6bits 1-8none---- 23 4246 -d-bits 1-8none---- 24 4439 1 - bits 1-7 bit 8 - a b d
- 63 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers frame alignment the selection of the bits for frame alignment is determined by the value written to control bits syc1 and syc0 (bits 4 and 3 in register x04h). the following table lists the options for selecting the f-bits that are used for frame alignment. out of frame alignment an out of frame (oof) alarm is declared when a specified number of errored bits is detected in a specified number of consecutive framing bits. the framing bits that are used for alignment are determined by the value written to control bits syc1 and syc0. the out of frame alignment is programmable using control bits oof1 and oof0 (bits 7 and 6 in regis- ter 04h). the following table lists the options for declaring an out of frame (oof) alarm. the qt1f- plus device supports offline framing. it continues to send data to the terminal side output while the framer is in the process of determining whether it has lost frame synchronization. if the framer goes back to in-frame, and the framing bit positions are not changed, the framer will continue passing the individual ds0 ? s through without affecting the data path. in the unlikely event that the framing bit position has been changed, the ds0 data path will be affected and a cfa alarm will be declared via registers x10h and x11h. framing pattern mimic during prbs payloads when prbs patterns are carried in the ds1 payload, the pattern may simulate (mimic) the framing pattern to some extent, with the risk of causing false frame synchronization. in the case of using esf with crc6, any mimic captured by the framer synchronizer will be rejected due to the mismatch of the crc6 calculation. therefore, any mimic will not affect framing with the esf format signal. when d4sf signal format is selected and a correct input signal framing format is applied, a mimic in the payload will not last longer than the framing pattern itself. therefore, the correct framing position should be detected. however, when the incoming signal does not comply with the d4sf framing format, the receive framer might capture the mimic. because the mimic will eventually run into mismatches, the framer will go out of frame again. in an experiment, sending an esf signal to a qt1f- plus programmed for d4sf with qrss in the payload caused from 4 to 6 oof events per second. syc1 x04h:4 syc0 x04h:3 d4 sf esf 0 0 not used not used 0 1 fs bits fps bits 1 0 ft bits not used 1 1 fs and ft bits fps bits and a valid crc-6 oof1 x04h:7 oof0 x04h:6 out of frame criteria 0 0 2 out of 4 framing bits in error 0 1 2 out of 5 framing bits in error 1 0 2 out of 6 framing bits in error 1 1 2 out of 4 framing bits in error
- 64 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers transmit framer each of the four transmit framers performs the following functions, unless the framer is configured for the transparent (unframed) mode of operation when the transparent mode only is selected. when the sf format is selected: - generate the framing (terminal - ft bits and signaling - fs bits) pattern - set the yellow alarm into bit 2 in all 24 ds0 channels or leave the bits for normal data - insert the 24 ds0 channels into the transmitted frame - insert the signaling states into bit 8 in all ds0 channels in frames 6 and 12 or leave the bits as is for clear channel operation when the esf format is selected: - generate the framing bit (fps bits) pattern - insert the 4 kbit/s hdlc link bits (d bits) into the f-bits - insert the calculated crc-6 value from the previous 24-frame superframe - insert the 24 ds0 channels into the transmitted frame - insert the signaling states into bit 8 in all ds0 channels in frames 6, 12, 18 and 24 or leave the bits as is for clear channel operation - calculate crc-6 for next superframe insertion please note that when a framer is configured for the transparent mode of operation, all the channels in the frame are transmitted from the data bus transparently through the qt1f- plus , bypassing the slip buffers. the sf format is selected by writing control bits fmd1 (bit 2) and fmd0 (bit 1) in register x04h to 01. the esf format is selected by writing control bits fmd1 (bit 2) and fmd0 (bit 1) in register x04h to 11. the selection is common to both the transmit and receive sides of a framer channel. the yellow alarm forces bit 2 to zero in all of the ds0 channels for the sf format (in place of data which can be either zero or one), while a repeating sequence of eight ones followed by eight zeros in the hdlc link is used in the esf format. the microprocessor can write the state of the yellow alarm indication. when the microprocessor writes a 1 to control bit yel (bit 2) in register x07h, the yellow alarm indication is transmitted for either the sf or esf format. in addition, when control bit enyel (bit 4) in register 00h is written with a 1, the yellow alarm indication from the signaling highway in the transmis- sion mode only will result in a yellow alarm indication being transmitted. the transmitted path for the data link bits (d-bits) in the esf format can be assigned from the signaling highway, hdlc link controller, or an internally generated 16-bit coded message. when control bit bfdl (bit 1) in register x01h is a 1, the bits are sent via the signaling highway. when control bit bfdl is 0, the bits are sent via the hdlc link controller. the selection of the d-bits from either signaling highway or the hdlc link controller can be overwritten by the yellow alarm indication generation or when the 16-bit coded message is enabled. the 16-bit coded message is generated for the esf format only when control bit ebt (bit 0) in register x08h is written with a 1. the 16-bit message consists of eight ones followed by a 0, a six-bit code, and another 0 (11111111 0xxxxxx0). the six-bit code word is written to control bits tbcd5-tbcd0 in register x0bh. each framer has the capability of generating framing pattern errors, and also crc-6 errors in the esf format. when con- trol bit frme (bit 3) in register x07h is written with a 1, the framer will generate and transmit one bad framing bit. the bit that is detected in error depends on the framing pattern selected in the receiver. when control bit crc (bit 4) in register x07h is written with a 1, the crc bits are transmitted inverted for one superframe. each framer is capable of sending sf loop-up and loop-down codes per ansi t1.403-1998. the specific loop-up code is provided by setting control bits lu6- lu0 (bits 6 - 0) in register 014h to the desired code and bits ulen1 and ulen0 (bits 4 and 3) in register 016h to the desired length. setting control bit txup (bit 5) in register x05h will cause the loop-up code to be sent on the line continuously in place of normal data and framing. the specific loop-down code is provided by setting control bits ld6- ld0 (bits 6 - 0) in register 015h to the desired code and bits dlen1 and dlen0 (bits1 and 0) in register 016h to the desired length. setting control bit txdn (bit 4) in register x05h will cause the loop-down code to be sent on the line continuously in place of normal data and framing.
- 65 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers channels 1-24 channels 1-24 are inserted into the transmitted frame from the slip buffer when it is enabled, or directly from the data high- way when it is bypassed (transmission mode only). the slip buffer locations are registers x90h - xa7h (frame 1) and xa8h - xbfh (frame 2). an individual time slot in the buffer can be frozen by writing a 0 to one or more control bits tde1- tde24 in registers xe4h - xe6h. this permits the microprocessor to write idle or service codes for one or more ds0s. fast sync mode the qt1f- plus provides a fast sync mode which may be used for testing purposes. the fast sync mode for the receiver side is selected when control bit rxfs (bit 1) in register x06h is written with a 1 in the nrz mode. a pulse that is one clock cycle wide in bit position 192 of the last frame forces the framer into synchronization. it can occur repetitively at 3 m s intervals for the esf format or at 1.5 ms intervals for the sf format, or it can be pulsed once provided the received framing sequence is valid afterwards. the fast sync mode for the transmitter side is selected when control bit txfs (bit 0) in register x06h is written with a 1 in the nrz mode. the tfsn output in this mode is a one clock cycle wide pulse in bit position 192 of the last frame in the multiframe that occurs every 3 ms for the esf format or every 1.5 ms for the sf format. this allows an external device to be synchronized to the qt1f- plus framer. slip buffers each framer contains a two-frame slip buffer in both the transmit and receive data directions. either of the slip buffers can be bypassed, if required, in the transmission mode only. the slip buffers must be enabled in the mvip mode. only the transmit and receive data time slots (ds0 channels 1-24) are passed through the slip buffers. the signaling states and framing bits are buffered in a separate memory location and are not subjected to slips. each buffer is organized as a circu- lar queue two frames in length. at this point, if data is arriving faster than it is being removed, the buffer will begin to fi ll. before the buffer becomes totally full, a controlled slip will occur and one frame of data will discarded. this is accom- plished by moving the write pointer back one frame and overwriting the previous frame that was written. if, after recenter- ing, the data is being removed faster than it is arriving, the buffer will begin to empty. before the buffer becomes completely empty, a controlled slip occurs in the opposite direction, and a frame of data is added to the buffer. this is accomplished by moving the read pointer back one frame and repeating the last frame sent. each buffer may be manu- ally recentered by setting the tsr or rsr control bits (bit 2 and 1) in the framer clock control register x02h. the transmit slip buffer is used to absorb low speed jitter in the transmit direction. the transmit slip buffer is enabled by writing a 1 to control bit tse (bit 4) in the framer clock control register x02h. when enabled, time slots are written into the transmit slip buffer by the system clock (tclkn), and read out by the recovered receive clock (lrclkn), the system clock (tclkn), or the local oscillator (lo). control bits txc1 and txc0 (bits 7 and 6) in register x02h select the clock source. the time slots (t = 1-24) from the transmit data bus are written into the slip buffer when their respective enable bits (tdet) in registers xe4h, xe5h and xe6h are written with a 1. if a phase shift between the two clocks is detected, a deletion or repetition of one frame of data (24 ds0s) occurs by the buffer reaching an almost full or almost empty threshold. a transmit slip error is indicated by status bit txslip (bit 1) in register x10h, with a latched event ltxslip (bit 1) indicated in register x11h. the transmit slip buffer status is indicated by reading status bits txs1 and txs0 (bits 7 and 6) in register x14h which indicate if a slip has occurred and if it is a rep- etition or deletion. please note that the slip buffer alarms remain active when the slip buffer is disabled.
- 66 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers the individual ds0 channels in both frames can be accessed by the microprocessor, as well as written by the micropro- cessor in place of data. when a ds0 channel enable control bit in register location xe4-xe6h is written with a 0, the con- tent of the two-frame slip buffer location is frozen. the microprocessor can write an idle or service code to be transmitted to the line. the transmit slip buffer data locations are x90h (channel 1) to xa7h (channel 24) for frame 1, and xa8h (channel 1) to xbfh (channel 24) for frame 2. please note that both buffer locations (i.e., frame 1 and frame 2) must be written with the service or idle code. a simplified schematic of the transmit slip buffer is shown in figure 35 . figure 35. transmit slip buffer the receive slip buffer is used when the receive clock (rclkn) is provided from an external source. the receive slip buffer controls the time slot access and retiming, providing a two-frame buffer that is optionally bypassable in the trans- mission mode only. the slip buffer must be enabled in mvip mode. time slots from the line interface are written into the slip buffer by the recovered receive clock (lrclkn), and read out by the system clock (rclkn). if a phase shift between the two clocks is detected, a deletion or repetition of one frame of data (24 ds0s) occurs by the buffer reaching an almost full or almost empty threshold. the time slots from the receive line signal are written into the slip buffer when their respec- tive enable bits (rden) in registers xe0h, xe1h and xe2h are written with a 1. individual ds0 channels can be accessed by the microprocessor, and they can be written by the microprocessor in place of data. when a ds0 enable control bit in register location xe0-xe2h is written with a 0, the content of the two-frame slip buffer location is frozen. the microprocessor can write an idle or service code in the location that will be transmitted to the receive data highway. the receive slip buffer data locations are x40h (channel 1) to x57h (channel 24) for frame 1, and x58h (channel 1) to x6fh (channel 24) for frame 2. please note that both buffer locations (i.e., frame 1 and frame 2) must be written with the service or idle code. a simplified schematic of the receive slip buffer is shown in figure 36 . tr a n s m i t slip buffer slip buffer control 0 1 0 1 2 divide by 193 tse (bit 4 in x02h) transmit data txc1, txc0 lo tclkn lrclkn synchronization tsr note: n is the framer number (1, 2, 3, 4) (bit 2 in x02h) tclkn tdatan tsyncn qt1f- plus (local oscillator) (control bits, bits 7 and 6 in x02h) framer n
- 67 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers a receive slip error is indicated by status bit rxslip (bit 0) in register x10h, with a latched event lrxslip (bit 0) indi- cated in register x11h. the receive slip buffer status is indicated by reading status bits rxs1 and rxs0 (bits 5 and 4) in register x14h which indicate if a slip has occurred and if it is a repetition or deletion. figure 36. receive slip buffer delay delay through the qt1f- plus is a function mainly of the slip buffers, though other factors also influence the amount of delay. the table below gives the typical delay for different elements of the framer from line to system and from system to line. all numbers are in bit times for a clock rate of 1544 khz. to estimate the total delay through a framer, add the system interface delay to the slip buffer delay (choose enabled or disabled value) and the codec delay (choose nrz, ami or b8zs value), and then multiply by 648 ns. note 1: when the framer is reset, the nominal delay is 96 bits through the slip buffer. recenter (control bit rsr toggled) will cause a slip if the delay exceeds 289 bits to minimize the delay. note 2: when the framer is reset, the nominal delay is 96 bits through the slip buffer. recenter (control bit tsr toggled) will cause a slip if the delay exceeds 289 bits to minimize the delay. direction of signal flow system interface slip buffer codec (select one) disabled enabled nrz ami b8zs rposn/ rldatn to rdatn 1 4 8 to 378 (note 1) 11 8 tdatn to tposn/ tldatn 1 4 8 to 378 (note 2) 11 8 receive slip buffer slip buffer control 0 1 rdatan rsr note: n is the framer number (1, 2, 3, 4) (bit 1 in x02h) rclkn receive data rsyncn qt1f- plus rse rxc (bit 5 in x02h) lrclkn recovered sync (bit 3 in x02h) framer n
- 68 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers signaling the signaling states are carried in bit 8 in the ds0 channels in frames 6 and 12 for the sf format and frames 6, 12, 18 and 24 for the esf format. control bits typ1 (bit 7) and typ0 (bit 6) in register 03h select the signaling format to be carried. clear channel capability is also selectable by written these control bits with a 00. the sf format carries 2-state, 4-state or 9-state signaling. 2-state signaling (a bits) is carried in frames 6 and 12. for 4-state and 9-state signaling, the a bit states are carried in frame 6, and the b bit states are carried in frame 12. the esf format carries 2-state, 4-state or 16-state signaling. 2-state signaling (a bits) is carried in frames 6, 12, 16 and 24. for 4-state signaling, the a bit states are carried in frames 6 and 18, and the b states are carried in frames 12 and 24. for 16-state signaling (only for the esf format), the a state is carried in frame 6, the b state in frame 12, the c state in frame 18, and the d state in frame 24. in the TXC-03103C, the transmit and receive signaling buffers can be used the same way for both ab signaling in sf and abcd signaling in esf modes, provided the framing mode is set to sf, and the signaling type is set to 16-state, under which condition all the abcd sections of the 96-bit buffer are used to read out and write in signaling bits even for the sf framing mode, unlike the txc-03103 device. in effect, the ab signaling bits from the 6th and 12th frame of the "m"th 12-frame sf are stored in the a,b sections of the buffer, while the ab signaling bits from the 6th and 12th frames of the "m+1"th 12-frame sf are stored in the c,d sections of the buffer. this allows monitoring and inserting of the a/b bits for toggle during every sf in the 9-state signaling scheme, as per the requirements of ansi t1.403. if the sf format 9-state signaling scheme is used, the control bits fmd1 and fmd0 (bits 2 and 1 in regis- ter x04h) will have to be set to 01, and the typ1 and typ0 bits (bits 7 and 6 in register x03h) will have to be set to 11. the following diagram illustrates this rx signaling ram tx signaling ram b c d a a b c d 612612 sf superframe n sf superframe n+1 612612 sf superframe n sf superframe n+1 rsigln in mvip mode tsigln in mvip mode a b c d a b c d } } { {
- 69 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers signaling buffers the transmit and receive signaling buffers that are used to interface the qt1f- plus to the system are 96 bits in length. in the receive direction, the signaling bits are extracted from the data stream and placed in the receive signaling buffer after the framing sequence is detected in the receive framer block. a simplified schematic of the receive signaling buffer is shown in figure 37 . in the transmission mode, four signaling bits are sent each frame, and all signaling states are sent over the 24 frames. receive signaling bits are clocked out by the system clock (rclkn), which is sourced by either the system or the qt1f- plus . the signaling bits on rsigln are sent such that they will meet the system requirements for for- matting a virtual tributary (vt) in a sonet format in the next multiframe. these bits can be extracted using the receive sync signal rsyncn. in the mvip mode, all the signaling bits are sent for every ds0 channel every frame (125 microsec- onds) from the receive signaling buffer by using the system clock (rclkn) and sync pulse (rsyncn). figure 37. receive signaling buffer parallel to serial read address rx signaling ram data addr write address from framing hardware recovered rxsync recovered rxfsync cpu data cpu addr rclkn rsyncn rsigln 4 5 5 5 5 note: n is the framer number (1, 2, 3, 4) qt1f- plus framer n i/o
- 70 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers the received signaling bits are stored sequentially in the receive signaling buffer in the order they are received. the sig- naling bits in the receive signaling buffer (register locations x80h, x81h, x82h, x84h, x85h, x86h, x88h, x89h, x8ah, x8ch, x8dh and x8eh) may be read at any time by the microprocessor in order to monitor the signaling states, or writ- ten to modify the outgoing values. since the buffer is accessed by multiple asynchronous processes, the read and write cycles for the signaling buffer are synchronized to the internal clocks. simultaneous accesses are serviced sequentially. the priority of service depends on the amount of latency acceptable between when the request was received and when the data is required to be available. when the corresponding (receive and transmit) signaling enable bits (se1-se24 bits) in register locations xe8h (channels 1 - 8), xe9h (channels 9 - 16), and xeah (channels 17 - 24) are written with a 1, the signaling bits are sent on the signaling highway (and data highway). for example, a 1 written to control bit se1 enables the signaling bits for ds0 channel 1 to be written into the signaling buffer. when a 0 is written into control bit se1, the sig - naling buffer for channel 1 signaling is set to 0. the abcd=0 states will be sent on the signaling highway until the se1 bit is written with a 1. please note that the action of the receive signaling freeze control bit, rxf, that acts on all 24 ds0s (bit 5 in register x03h) is different. when rxf is set to 1, it freezes the receive signaling buffer, and the contents cannot be changed from the receive line (but the microprocessor can write a new signaling value to the buffer) and the receive signaling highway gets the frozen signaling states in the buffer. when rxf is set to 0, the signaling highway updates with the values from the receive line the signaling bits in the receive direction are automatically frozen in their present states when loss of signal or loss of syn - chronization occurs. a signaling freeze may also be initiated manually by writing a 1 to control bit rxf (bit 5) in register x03h. a receive signaling freeze indication is given by status bit rxsf (bit 7) in register x15h. a simplified schematic of the transmit signaling buffer is shown in figure 38 . transmit signaling bits on the signaling pin tsigln are clocked into the transmit signaling buffer using the transmit system clock tclkn and sync pulse tsyncn. in the transmission mode, four signaling bits are provided each frame. in the mvip mode, all signaling bits are written to the tx signaling ram for every channel every other frame (250 microseconds). however, signaling from the signaling high- way must be provided every frame. figure 38. transmit signaling buffer serial to parallel write address tx signaling ram data addr read address to framing hardware txsync txfsync cpu data cpu addr tclkn tsyncn tsigln 4 5 5 5 5 note: n is the framer number (1, 2, 3, 4) qt1f- plus framer n i/o
- 71 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers the transmit signaling bits from the signaling highway are stored sequentially in the transmit signaling buffer in the order they are received. the signaling bits in the transmit signaling buffer (register locations xd0h, xd1h, xd2h, xd4h, xd5h, xd6h, xd8h, xd9h, xdah, xdch, xddh and xdeh) may be read at any time by the microprocessor in order to monitor the signaling states, or written to modify the outgoing values. since the buffer is accessed by multiple asynchro- nous processes, the read and write cycles for the signaling buffer are synchronized to the internal clocks. simultaneous accesses are serviced sequentially. the priority of service depends on the amount of latency acceptable between when the request was received and when the data is required to be available. when the corresponding signaling enable bits (se1-se24 bits) in register locations xe8h (channels 1 - 8), xe9h (channels 9 - 16), and xeah (channels 17 - 24) are written with a 1, the signaling bits are written into the transmit data stream in the corresponding robbed bit positions. for example, a 1 written to control bit se1 enables the corresponding abcd signaling bits from the transmit signaling buffer for channel 1 to be written into the lsb of ds0 1 in frame numbers 6, 12, 18 and 24. when a 0 is written into control bit se1, the signaling buffer for channel 1 signaling is prevented from writing to the line, although the buffer updates from the transmit signaling highway. the action of the transmit signaling freeze control bit, txf (bit 4 in register x03h), that oper- ates on all 24 ds0s, is different. when txf=1, the transmit signal buffer becomes frozen to its current states, and contin- uously updates the line with the frozen signaling states. the frozen signaling states can be changed by the microprocessor, but they cannot be updated from the transmit signaling highway. when txf=0, only then can the trans- mit signal buffer update from the highway. a transmit signaling freeze indication occurs when control bit txf (bit 4) in register x03h is written with a 1 (manual freeze), or when ais is detected on the signaling highway (transmission mode only). a transmit signaling freeze indica- tion is given by status bit txsf (bit 6) in register x15h. clocking and synchronization the clocking and synchronization portion of the qt1f- plus includes the receive clock configuration, transmit clock syn- chronization, and the slip buffers for each of the framers. the following table provides a summary of the rclkn clock operation in the receive direction. * note: control bit rxc (bit 5) in the framer clock control register x02h configures rclkn as an input or output for each of the framers. in the mvip mode, the system clock must be an input. in the transmit direction, the system clock tclkn and sync pulse tsyncn are always inputs to the qt1f- plus . the transmit data tdatan is clocked out of the slip buffer by either the transmit system clock (tclkn), the local oscillator input (lo), or the recovered receive clock (lrclkn). the clock selection for each framer is controlled by txc1 (bit 7), and txc0 (bit 6) in framer clock control register x02h. the local oscillator input (lo) has a nominal frequency of 1.544 mhz and should be accurate to + 32 ppm. lo is the source for the rclkn output when rxc = 1 and los is detected. the following table provides a summary of the tclkn clock operation in the transmit direction. interface mode clock rate sync edge in data/sig edge out comments transmission 1.544 mhz pos. neg. clock and sync pulse may be outputs* in which rclkn clock is derived from the recovered received clock (lrclkn). mvip 2.048 mhz pos. pos. system clock and sync pulse must be inputs. interface mode clock rate sync edge in data/sig edge in comments transmission 1.544 mhz pos. pos. mvip 2.048 mhz pos. neg.
- 72 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers clock reference for system applications that require the recovered receive clock, the qt1f- plus can provide two reference clocks derived from any of the four clock inputs (lrclkn), when enabled. the recovered receive clock input lrclkn that is used to derive the reference clock clkref1 (pin 46) is determined by the value written to control bits cr1s1 and cr1s0 (bits 1 and 0) in the clock reference selection register (019h). the recovered receive clock that is used to derive the reference clock clkref2 (pin 2) is determined by the value written to control bits cr2s1 and cr2s0 (bits 7 and 6) in the clock reference selection register (019h). the following table lists the various conditions for enabling/disabling the clock refer- ence signal on the clkref1 pin. the enref1 and 1544khz control bits are located at bits 3 and 4 in the clock refer- ence selection register (019h). the lie control bit (bit 1) is located in the frame configuration register (x00h). the los alarm status bit (bit 7) is located in the ds1 status register (x10h). x can be either state. the following table lists the various conditions for enabling/disabling the clock reference signal on the clkref2 pin. the enref2 and 1544khz control bits are located at bits 5 and 4 in the clock reference selection register (019h). the lie control bit (bit 1) is located in the frame configuration register (x00h). the los alarm status bit (bit 7) is located in the ds1 status register (x10h). x can be either state. enref1 (control) los(n) (alarm) lie(n) (control) 1544khz (control) action 0 x x x clkref1 pin tristated. 1 0 0 0 8 khz reference provided on clkref1. the 8 khz signal is derived from the recovered clock that is selected (lrclkn). 1 0 0 1 1544 khz reference provided on clkref1. the 1544 khz signal is derived from the recovered clock that is selected (lrclkn). 1 1 x x clkref1 pin is forced low. 1x 1 x clkref1 pin is forced low when lintn is in the active true state. enref2 (control) los(n) (alarm) lie(n) (control) 1544khz (control) action 0xxx clkref2 pin tristated. 1 0 0 0 8 khz reference provided on clkref2. the 8 khz signal is derived from the recovered clock that is selected (lrclkn). 1 0 0 1 1544 khz reference provided on clkref2. the 1544 khz signal is derived from the recovered clock that is selected (lrclkn). 1 1 x x clkref2 pin is forced low. 1x 1 x clkref2 pin is forced low when lintn is in the active true state
- 73 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers ais detection and generation a line ais is detected when the received line signal has 99.9% or more ones present in a period of 48 ms. recovery occurs when fewer than 99.9% of ones occur in a 48 ms period. the status of line ais is given by the ais status bit (bit 0) in register x1bh. ais-ci detector to meet the latest ansi t1.403 core requirements, the TXC-03103C detects the ais-ci signature when ais is present. the ais-ci signature is a pattern whose length is 6176 bits, with all bits being logical ones except bit number 0, bit number 3088, bit number 3474 and bit number 5760, which are logical zeros. it may also be viewed as a pattern which recurs at 386-bit intervals that is 1111 1111 0011 1110 (from left to right) that is log- ically and-gated with an all ones pattern. the actual ais-ci code is a1.260 second period in which the ais-ci signature is present for 150 milliseconds and a regular ais is present for 1.110 seconds. detection of the ais-ci signature pattern twice in a row is sufficient to declare ais-ci. a single bit error in the pattern, once the pattern is detected, is ignored. the output of the ais-ci signature detector is logically and-gated with the out- put of the ais detector. this combined signal is logically or-gated with the change of frame alignment alarm, cfa, register (bit 3 in register x110h). mask mcfa, latched value lcfa, performance value pcfa and fault value fcfa are all bit 3 of registers x09h, x11h, x12h and x13h, respectively. these bits are shared with the ais-ci signature function. global mask and global events for cfa also apply to ais-ci. bit 3 of register 00ah (global status indication register) is a 1 when any of the four framer channels has detected a change in frame alignment or the ais-ci signature. when bit 3 in register 00bh is set to a 1, a change in the frame alignment or ais-ci indication in any framer channel (lcfa/laisci, registers x11h), is masked from providing an interrupt indication. the qt1f- plus also provides control bits and enable bits for alarms to generate ais for the receive highway. when con- trol bit svtais (bit 6) in register x07h is written with 1, the ais, oof and los alarms, if enabled by their respective enais (bit 2), enoof (bit 1), and enlos (bit 0) control bits in the signaling and time slot control register x03h, cause the generation of ais according to the following table. the table reflects the ais actions taken on out of frame (oof) alarm when enabled by enoof and svtais. control bits enais for ais and enlos for loss of signal function in the same manner. please note that the microprocessor can force ais to be generated for the receive data highway indepen- dent of the three control bits by writing a 1 to control bit sysall1 (bit 5) in register x07h. transmission mode mvip mode enoof svtais action 0 0 normal operation. no ais generated on signaling or data highway. 0 1 normal operation. no ais generated on signaling or data highway. 1 0 ais generated only on signaling highway when oof alarm is detected. a-bits on the signaling highway are equal to 1. 1 1 ais generated on signaling and data highways when oof alarm is detected. a-bits on the signaling highway are equal to 1. enoof svtais action 0 0 normal operation. no ais generated on data highway. 0 1 normal operation. no ais generated on data highway. 1 0 normal operation. no ais generated on data highway when oof alarm is detected. 1 1 ais generated on data highway when oof alarm is detected.
- 74 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers in the transmit direction, from the transmit highway to the line, line ais can be generated. when the microprocessor writes a 1 to control bit aise (bit 1) in register x07h, the all ones ais pattern is transmitted in all bits of the frame continuously until the control bit is written with a 0. when the microprocessor writes a 1 to control bit ensais (bit 2) in register x00h, i n the transmission mode only, the all ones ais pattern is transmitted in all bits of the frame when the a-bits in the signaling highway are detected as ones. in addition, a status bit vtais (bit 3) in register x14h indicates when the a-bits are set to 1 in the transmission mode. ansi rai - ci detector in accordance with ansi t1.403 core requirements, rai-ci for the esf format is transmitted using the fdl, by sequentially interleaving 0.99 s of the unscheduled message 1111 1111 0000 0000 (left to right; which represents rai in the fdl), with 90 ms of the message 1111 1111 0111 1100 (left to right). rai-ci for the sf format is detected if all 24 time slots consist of the pattern 1000 1011 (left to right). for sf format, if rai/yellow alarm is detected (bit 2 of all ds0s = 0, control bits fmd1 and fmd0 in register x04h = 01), sf rai-ci (x0xxxxxx per ds0 for all 24 ds0s) may be detected by reading the receive slip buffer contents (rds0(1)-rds0(24) for frames 1 and 2, at register locations x40h-x6fh). hdlc channel a hdlc message frame is composed of four parts: an opening flag, the message (which consists of multiple bytes), a two-byte crc-16 frame check sequence, and a closing flag, as shown in figure 39 below. figure 39. hdlc format the opening and closing flags are represented by a single, unique 8-bit character defined as 01111110, which contains six contiguous ones. to avoid the occurrence of a false flag within the data stream, a zero is inserted (stuffed) after each string of five contiguous ones in the message or crc-16. reception of more than six contiguous ones is interpreted as a frame abort sequence. when an abort sequence is received, the remainder of the current frame is ignored and the received portion is discarded as an invalid frame. a two-byte crc-16 frame check sequence is computed across the con- tents of the message (after the opening flag), and appended to the end of the message. the time between consecutive frames is filled with one or more flags. when two or more flags occur in sequence, they may share the boundary zero between them (011111101111110). a 16-byte fifo is provided in each direction for each framer, which permits short messages to be transmitted and received without having the microprocessor service the fifos. for long messages, interrupts and status information are provided to facilitate fifo servicing by the microprocessor. for both short and long messages, the hdlc link controller performs the following functions: - zero bit stuffing/destuffing (11111 to 111110 / 111110 to 11111) - itu-t crc-16 generation/checking (16-bit sequence) - flag generation/detection (01111110) - abort generation/detection (01111111...) - start of frame detection - end of frame detection - fifo overflow and underflow bit87654321 opening flag 0 1 1 11110 message address and control information crc-16 closing flag01111110
- 75 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers the hdlc receiver is enabled when a 1 is written to control bit ehr (bit 7) in the hdlc link control register x08h. when enabled, the hdlc receiver will remove the stuffed zero bits, search for the opening flag and place the message contents in a 16-byte fifo. the hdlc link controller will compute a crc and compare it against the crc that is received. the received crc is not stored in the fifo and is discarded after being received. the receive fifo is monitored for fill level, with maskable interrupts and latched indications provided. bits rxfs1 and rxfs0 (bits 3 and 2) in the hdlc link status register x16h indicate when the receive fifo is less then half full, equal to or greater than half full, full and overflowed. an interrupt may also be set at the end of the message, or when the fifo is half full, using the rhie control bit (bit 3) in the hdlc link control register x08h. thus, when the messages are always expected to be shorter than the maximum fifo depth of 16 bytes, the hdlc link controller will generate an inter- rupt on the completion of the message. when the messages are expected to exceed the maximum fifo depth of 16 bytes, the controller will generate an interrupt when the fifo is half filled. bits c4-c0 (bits 4-0) in the hdlc link receive data register (x18h) provide the number of bytes presently stored in the receive fifo. bits rhis2-rhis0 (bits 7-5) in the hdlc link status register (x16h) provide message status and error indications, including when a bit code message is received. the hdlc link controller will generate a maskable interrupt for start of message detected, valid message received, crc in error, and message aborted. the message bytes are read by the microprocessor at bits rhd7-rhd0 in register x17h for each framer. bit 0 corresponds to the first bit received in a byte. the latest ansi t1.403 core requirements allow performance messages to share the facility data link with the minimum spacing between messages to be a single lapd flag character. this is different from the previous design constraints of one message per second or command and response message traffic. the txc-03103 design resets the receive fifo when the start of a new message is detected. the TXC-03103C design waits until the first byte of the received non-flag character following one or more flag characters (01111110) is col- lected to reset the receive fdl fifo. the figure below describes the change as viewed from the 4 kbit/s data link. by delaying the fifo reset the minimum time between the fdl interrupt and fifo reset is extended from 2 bits on the fdl link (500 micro- seconds) to 8 bits on the fdl link (2.0 milliseconds). this provides enough time for the attached microproces- sor to service the interrupt and read out the fdl fifo prior to the receipt of a back-to-back follow-on message. the hdlc transmitter is enabled when a 1 is written to control bit eht (bit 6) in the hdlc link control register x08h. when enabled, the hdlc link controller will transmit flags until data is placed in the transmit fifo. up to 16 bytes can be placed in the 16-byte fifo. the message bytes are written into bits thd7-thd0 in the hdlc link transmit data regis- ter x0ah. bit 0 corresponds to the first bit transmitted. the transmit bytes are read from the transmit fifo and a 16-bit crc is computed until the end of message is detected. when the last byte of the message is written into the fifo, the microprocessor will set the end of message status bit eom (bit 4) in the hdlc link control register x08h. the com- puted 16-bit crc will be appended to the end of the message followed by at least one flag before another message is transmitted. when the transmit fifo is emptied without setting the eom bit, the fifo will set an underflow indication, and an abort character will be transmitted, thereby terminating the message. crc crc 0 1 1 1 1 1 1 0 d d d d d d d d d d d d d d d d d d d d d d d d end of message n - 1 (e.g., prm) end of message detected, crc-16 checked, message status determined and interrupt generated. txc-03103 clears fifo TXC-03103C clears fifo start of message n (e.g., nprm)
- 76 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers the transmit hdlc link controller provides latched event bits and maskable interrupt bits related to the transmit fifo sta- tus. information such as underflow and fill status is provided by reading status bits txfs1-txfs0 (bits 1-0) in the hdlc link status register x16h. transmit hdlc fifo service interrupts may be programmed to occur when the transmit fifo is half empty, or when the last byte is sent, by setting control bit thie (bit 2) in register x08h. for short messages, the entire message may be writ- ten into the fifo, and the controller will generate an interrupt, indicated by status bit this (bit 4) in register x16h, when the message has been sent. for longer messages, the controller will generate an interrupt when the fifo is ready to accept more data. there are four general types of message transfers, which are described below: transmitting long and short messages, and receiving long and short messages. the difference between the long and short messages is primarily in how the 16- bit fifos are serviced. with short messages, the entire message will fit into the fifos and interrupts will be generated when the end of the message occurs. with long messages, the message will not fit into the fifo, and the message will have to be transmitted or received in several segments. since long and short received messages are similar, their pro- cessing is described under the same heading. transmit short message to transmit a short message, first configure the transmitter to generate an interrupt at the end of message by writing a 0 to control bit thie (bit 2) in the hdlc link control register x08h. then write a 1 to control bit eht (bit 6) in register x08h to enable the transmitter. the hdlc link controller will transmit flags until data is written into the transmit hdlc fifo. write the message into the transmit fifo by writing each byte in turn to thd7-thd0 in register x0ah. bit 0 represents the first bit in the byte to be transmitted. the bytes written into thd7-thd0 are transferred automatically into the fifo. after the last byte is written into the fifo, the eom (bit 4) in register x08h is written with a 1. the transmitter will then begin to send the message bytes until the fifo is empty. since the eom bit was set, the completion of the message will generate an interrupt, if not masked, indicated by the latched this status bit ethis, (bit 4) in register x0eh. this latched status indication indicates that the message is complete or the fifo is half full. after the crc-16 is sent, the hdlc link controller will start to send flags. transmit long message to transmit a long message, first configure the transmitter to generate an interrupt at the half full level of the fifo by writ - ing a 1 to control bit thie (bit 2) in the hdlc link control register x08h. then write a 1 to control bit eht (bit 6) in regis- ter x08h to enable the transmitter. the hdlc link controller will transmit flags until data is written into the transmit hdlc fifo. write the first 16-byte message segment into the transmit fifo by writing each byte in turn to thd7-thd0 in register x0ah. bit 0 represents the first bit in the byte to be transmitted. the bytes written into thd7-thd0 are transferred auto- matically into the fifo. the hdlc link controller will then start to send the message bytes. when the fifo empties to the half full level, the ethis bit (bit 4) in register x0eh will be latched, and an interrupt generated, if the corresponding mask bit mthis (bit 4) in register x0fh is set to 0. this is an indication for the microprocessor to write another 8 bytes into the transmit hdlc fifo. this process of sending and refilling is repeated, 8 bytes at a time, until the last byte in the message is written into the fifo, when the eom (bit 4) in register x08h is written with a 1. the transmitter continues to send the final message bytes until the fifo is empty. when the last byte is transmitted and the fifo is empty, the ethis bit will latch while eom=1, indicating completion of the message. after the crc-16 is sent, the hdlc link controller will start to send flags. the latched event register x0eh should be cleared before sending the next message to enable the reception of the status of the next transmitted message. status bits txfs1-txfs0 (bits 1-0) in register x16h indicate the fill level of the transmit fifo.
- 77 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers receive message to receive a message, first configure the receiver to generate an interrupt at the half full level of the fifo by writing a 0 t o control bit rhie (bit 3) in the hdlc link control register x08h. then enable the receiver by writing a 1 to control bit ehr (bit 7) in register x08h. set mask bits mrhis2-mrhis0 (bits 7-5 in control register x01fh) to 001 and mrxfs1- mrxfs0 (bits 3-2 in control register x0fh) to 00. the receiver will generate an interrupt (provided the corresponding mask bit is written with a 0), when the fifo is half full or when an end of message is detected. interrupts from rhis2-rhis0 will only be generated for an end of normal mes- sage, a received message error or bit code received. interrupts from rxfs1-rxfs0 indicate fifo service is needed. the receive message is read from the fifo by reading the bytes rhd7-rhd0 in register x17h. bit 0 represents the first bit in the byte to be received. the bytes in rhd7-rhd0 are transferred automatically from the receive fifo. when the interrupt occurs, the rhis2-rhis0 status bits (bits 7 - 5) and rxfs1-rxfs0 (bits 3-2) in register x16h are also set in the erhis2-erhis0 bits (bits 7-5) and erxfs1-erxfs0 (bits 3-2) in the latched register x0eh, indicating the message sta- tus. if the message in progress status is set, the microprocessor should read the message bytes from rhd7-rhd0 using the fifo depth bits c4-c0 in register x18h to detect the number of bytes stored in the receive fifo. please note that the fifo depth count is updated when the event indication is latched and interrupt generated, and will not be modified until it is read and cleared by the microprocessor. during long messages, the count is allowed to change after the half full indica- tion. if the microprocessor fails to read out the fifo in time, a second interrupt indication is generated, indicating a full o r overflow condition. the reason for interrupt is indicated by status bits rxfs1-rxfs0 (bits 3-2) in register x16h. these control bits provide status information about the fill level of the receive fifo. an end of message is also indicated by the rhis2-rhis0 status bits. alarms the following line level alarms for each of the four framers are detected in the qt1f- plus : loss of signal (los), alarm indication signal (ais), out of frame (oof), yellow alarm indication (yel), change of frame alignment (cfa), severely errored frame (sef), transmit slip (txslip) and receive slip (rxslip). these alarms are provided by the ds1 status and mask registers (registers x09h-x13h). in addition, the following hdlc link level alarms are supported by the qt1f- plus : receive hdlc event and status, transmit hdlc event and status, receive fifo event and status, and transmit fifo event and status (registers x0eh and x16h). each hdlc event bit can cause an interrupt when the cor- responding mask bit is set to 0 in register x0fh. the latched status event indication (which can also be referred to as a software interrupt indication) for an alarm or condition is latched on either positive transitions, negative transitions, or bo th transitions. control bits rise (bit 6), and fall (bit 5) in the global configuration register 006h determine the transitions that cause an event bit to latch for all four framers, as shown in the following table: rise (bit 6) fall (bit 5) action 0 0 latched status bit indications in all registers disabled. hardware and software interrupt indications disabled. 1 0 latched status indication sets on positive alarm transition, along with generating a hard- ware interrupt provided the corresponding mask bit and the global interrupt status indica- tion bit gim (bit 7 in register 006h) are both 0. 0 1 latched status indication sets on negative alarm transition, along with generating a hard- ware interrupt provided the corresponding mask bit and the global interrupt status indica- tion bit gim (bit 7 in register 006h) are both 0. 1 1 latched status indication sets on both positive and negative alarm transitions, along with generating a hardware interrupt provided the corresponding mask bit and the global inter- rupt bit gim (bit 7 in register 006h) are both 0.
- 78 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers the latched event is cleared by writing a 0 to the associated bit position in the latched status indication register. the qt1f- plus also provides a global interrupt mask (gim) bit for the microprocessor interrupt pin (pin 125, int/irq ). when a 1 is written to control bit gim (bit 7) in the global configuration register 006h, this hardware interrupt indication pin is tristated when a latched indication (event) bit is set. when a 0 is written into the gim bit, the hardware interrupt pin is enabled. when enabled, the polarity of the interrupt pin can be inverted by writing a 1 to control bit ipol (bit 4) in the glo- bal configuration register 006h. besides providing individual unlatched and latched alarm status indications, and interrupt mask bits, on a per framer basis, the qt1f- plus provides global interrupt status indication bits, as well as global interrupt mask bits and framer pointer bits in the global register segment (registers 00ah-00eh). a global interrupt status indication bit is set to 1 in reg- ister 00ah if the same type of alarm occurs in any of the four framers, provided that the corresponding global mask bit in register 00bh is not set to 1 and the qt1f- plus is configured to latch on one of or both transitions of the alarm. registers 00ch and 00eh provide pointers to the framer which caused the line event or hdlc link event that triggered the interrupt. for example, assuming a loss of signal alarm occurred in framer 1 only, the los alarm will set the los bit (bit 7) in the unlatched register 110h. this alarm indication bit will be set to 1 for the duration of the alarm. assuming that control bits rise and fall (bits 6 and 5) in the global configuration register 006h are set to 10 (latched event set on a positive tran- sition), the transition from 0 to 1 of the los alarm will cause the llos bit (bit 7) in register 111h to latch. a hardware inte r- rupt will be generated on pin 125 if the interrupt mask bit mlos (bit 7) in register 109h is a 0, and the global interrupt mask bit gim (bit 7) in register 006h is a 0. if either of these bits is set to 1, the hardware interrupt will not occur. in additio n, the latched los indication will also cause a global los indication (bit 7) in register 00ah. the framer in which the loss of sig- nal alarm was detected can be found by reading bits 3-0 in register 00ch. the interrupt will be reset by first reading the llos latched alarm bit position (bit 7) in register 111h and then writing a 0 into the bit position. this will also clear the g lo- bal los indication bit. reading the register confirms that the loss of signal alarm occurred in framer 1. if the los alarm persists, it will not cause the latched bit position to relatch. the alarm status can be determined by now reading repeatedly the unlatched status bit (bit 7) in register 110h, until it becomes 0, indicating that recovery has taken place. shadow registers the qt1f- plus also provides shadow registers for the alarms of each of the four framers. the shadow register feature in the qt1f- plus is enabled by writing a 1 to the enable performance monitoring and fault monitoring control bit (enpmfm), bit 3 in the global configuration register 006h. by applying a pulse at one second intervals to t1si (pin 40), an indication bit will be set in register x12h if the corresponding alarm occurred at any time in the last one second interval. in addition, an indication bit will be set in register x13h if the alarm is active, but the transition to the active state did not occur in the last one second interval (i.e., the alarm has persisted for longer than one second). the rising edge of the t1si pulse will also reset a latched event bit position in register x11h independent of the microprocessor. figure 40 illustrates the operation of the shadow registers for a loss of signal (los) alarm for framer 1. the behavior shown in the diagram also applies to the other line signal alarms in the same registers (ais, oof, yel, cfa, sef, txslip, and rxslip). this figure assumes that control bits rise and fall (bits 6 and 5) in the global configuration register 006h are set to 10 (latched event set on a positive transition). please note that the los alarm causes a latched status indication llos (bit 7) in register 111h, and that the latched bit is reset by the rising edge of the t1si pulse. the plos status bit (bit 7) in register 112h is a 1 whenever there is a transition to los during the last one second interval or los is present at the end of the last one second interval. the flos status bit (bit 7) in register 113h is a 1 if the los alarm is active but did not become active during the previous one-second interval.
- 79 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers figure 40. shadow register operation in addition, shadow registers have been provided for monitoring the number of line errors that have occurred in one sec- ond intervals. when the enable pm/fm control bit (enpmfm), bit 3 in the global configuration register 006h, is a 1, the following shadow registers are updated with the count from the previous one-second interval on the rising edges of the one-second pulse provided at the t1si pin: a 9-bit register for a crc-6 error count, a 16-bit register for a coding violations count, and an 8-bit register for a framing bit error count. the rising edge of the one-second pulse also clears the counters that were holding the count for the transfer to the shadow registers. for example, the shadow register for monitoring frame bit errors in framer 1 works in the following way. the 8-bit framing bit error counter fbe7-fbe0 in register 1fch counts the number of frame bit errors over a one-second interval, which is determined by the t1si signal. at the rising edge of the pulse on the t1si pin, the count in register 1fch is transferred to the shadow register lfbe7-lfbe0 in location 1fah. the frame bit error counter in register 1fch is cleared at the same instant and it starts the error count for the next one-second interval. at the end of the next one-second interval, the shadow register is updated with the new count. a counter overflow bit fbeo is also provided (bit 7 in register 1fdh), with a corresponding shadow overflow bit lfbeo (bit 7) in register 1fbh. the microprocessor can also clear the counter in register 1fch by writing 00h to it. the shadow register holds its count during a microprocessor read cycle. maintenance the qt1f- plus provides three loopback modes. local, remote line, and payload remote loopbacks are available for each of the four framers. these three loopbacks allow the user to section a network path and isolate a specific failure. in addi- tion, a pseudo-random test generator and analyzer are provided. in-band loop-up and loop-down codes, per ansi t1.403-1998, are supported in both sf and esf modes. t1si los llos plos flos t=0 s t=1 s t=2 s t=3 s t=4 s t=5 s t=6 s (bit 7 in 113h) (bit 7 in 112h) (bit 7 in 111h) (bit 7 in 110h) (input on pin 40) note 1: for this example, latched events are set only on positive event transitions. note 2: plos = los + llos evaluated at one second boundaries (where ? + ? is a logical or). note 3: flos = los & llos evaluated at one second boundaries (where ? & ? is a logical and, and x is a logical inversion).
- 80 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers local loopback local loopback for a framer is enabled when a 1 is written to control bit llp (bit 0) in register x05h. local loopback con- nects the transmit path with the receive path in the direction toward the line, as illustrated in figure 41 below. the loop- back is independent of the line interface selected, nrz or dual unipolar (rail). when control bit tx1s (bit 2) in register x05h is written to 1, an ais (all ones signal) is transmitted to the line instead of data. please note that transmit line ais can be enabled independent of the local loopback feature. figure 41. local loopback remote line loopback remote line loopback for a framer is enabled when a 1 is written to control bit rlp (bit 1) in register x05h. remote line loopback connects the receive line data back to the transmitter, as illustrated in figure 42 below. the loopback is per- formed before the b8zs codec. the loopback is independent of the line interface selected, nrz or dual unipolar (rail). figure 42. remote line loopback the remote line loopback can be activated or deactivated by the reception of loop-up or loop-down codes on the line. these codes are described in ansi t1.403-1998 for the sf mode of operation. this feature is enabled by setting control bit enpmfm (bit 3) in register 006h to a 1, setting control bit alup (bit 6) in register x05h to a 1 and providing a one sec- ond pulse on pin t1si. the specific loop-up code is provided by setting control bits lu6-lu0 (bits 6 - 0) in register 014h to the desired code and bits ulen1 and ulen0 (bits 4 and 3) in register 016h to the desired length. if a matching pattern is received for 5 seconds the qt1f- plus channel will automatically enter the remote line loopback state and remain there until a loop-down code is received. the local microprocessor can determine if a channel is in loopback by reading status bits up (bit 2) and down (bit 1) in register x15h. the specific loop-down code is provided by setting control bits ld6- ld0 (bits 6 - 0) in register 015h to the desired code and bits dlen1 and dlen0 (bits1 and 0) in register 016h to the desired length. if a matching pattern is received for 5 seconds the qt1f- plus channel will automatically exit the remote line loopback state. 0 1 b8zs codec llp receive line 0 1 tx1s 1 ? s transmit line line interface internal receive data internal transmit data note: bold/dashed lines show paths used for tx1s=1 and llp=1. (if rail = 1) 1 0 rlp internal receive data internal transmit data transmit line receive line line interface note: bold/dashed lines show paths used for rlp=1. b8zs codec (if rail = 1)
- 81 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers ds0 channel loopback the ds0 channel loopback feature is enabled when a 1 is written to control bit ends0lb (bit 4 in register 0ffh). one or more ds0 channels can be looped back by writing a 1 to the corresponding control bit lbd24-lbd1 in registers x1eh, x1dh and x1ch. the loopback takes place after the slip buffer and is provided whether the receive slip buffer is enabled or disenabled. control bits ends0lb and lbd24-lbd1 are set to 0 upon a hardware reset. this function requires the presence of tclkn to operate correctly. payload remote loopback the qt1f- plus device provides two payload remote loopback mechanisms; one that is identical to the qds1f and one that is improved relative to the qds1f. for the qds1f style mechanism, setting control bit payl (bit 3) in register x05h provides this feature in a way that only the sequence integrity of the payload is kept. a small fifo is provide between the receive and transmit sides of the framer as shown in figure 43 below to account for skipping the receive frame bit and inserting the transmit frame bit. therefore, the framing bit position of the outgoing bit stream is changed relative to the pay - load signals of the incoming bit stream from the line. this loopback is performed before the receive slip buffer. in order to keep the framing bit and payload relation intact, the qt1f- plus also provides a payload remote loopback by enabling all 24 ds0 loopbacks. this function requires the presence of tclkn to operate correctly. in this way, the transmit data highway selects the data from the receive data payload through a buffer that permits received ds0c data to be mapped to transmit ds0c positions for c = 1 through 24, as shown in figure 43 below. figure 43. payload remote loopback 0 1 ends0lb transmit framer transmit line interface transmit line receive line line interface receive signaling receive data data & signaling highway transmit data transmit signaling and lbd24-lbd1 receive framer receive line interface buffer fifo payl 1 0 (8 bit)
- 82 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers boundary scan introduction the ieee 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the ieee joint test action group (jtag). boundary scan is a specialized scan architecture that provides observability and control- lability for the interface pins of the device. the test access port block, which implements the boundary scan functions, consists of a test access port (tap) controller, instruction and data registers, and a boundary scan register path border- ing the input and output pins, as illustrated in figure 44 . the boundary scan test bus interface consists of four input sig- nals (i.e., the test clock (tck), test mode select (tms), test data input (tdi) and test reset (trs ) input signals) and a test data output (tdo) output signal. the tap controller receives external control information via a test clock (tck) signal, a test mode select (tms) signal, and a test reset (trs ) signal, and it sends control signals to the internal scan paths. the scan path architecture consists of a two-bit serial instruction register and two or more serial data registers. the instruction and data registers are con- nected in parallel between the serial test data input (tdi) and test data output (tdo) signals. the test data input (tdi) signal is routed to both the instruction and data registers and is used to transfer serial data into a register during a scan operation. the test data output (tdo) is selected to send data from either register during a scan operation. when boundary scan testing is not being performed, the boundary scan register is transparent, allowing the input and out- put signals at the device pins to pass to and from the qt1f- plus device ? s internal logic, as illustrated in figure 44 . during boundary scan testing, the boundary scan register disables the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. a timing diagram for the boundary scan feature is provided in figure 20 . boundary scan support the maximum frequency the qt1f- plus device will support for boundary scan is 10 mhz. the qt1f- plus device per- forms the following boundary scan test instructions: - extest - sample/preload -idcode - bypass extest test instruction: one of the required boundary scan tests is the external boundary test (extest) instruction. when this instruction is shifted in, the qt1f- plus device is forced into an off-line test mode. while in this test mode, the test bus can shift data through the boundary scan registers to control the external qt1f- plus input and output leads. sample/preload test instruction: when the sample/preload instruction is shifted in, the qt1f- plus device remains fully operational. while in this test mode, qt1f- plus input data, and data destined for device outputs, can be captured and shifted out for inspection. the data is captured in response to control signals sent to the tap controller. bypass test instruction: when the bypass instruction is shifted in, the qt1f- plus device remains fully operational. while in this test mode, a scan operation will transfer serial data from the tdi input, through an internal scan cell, to the tdo pin. the purpose of this instruction is to abbreviate the scan path through the circuits that are not being tested to only a single clock delay. idcode test instruction: the format of the idcode test instruction is "10".
- 83 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers boundary scan reset specific control of the trs pin is required in order to ensure that the boundary scan logic does not interfere with normal device operation. this pin must either be held low, asserted low, or asserted low then high (pulsed low), to asynchro- nously reset the test access port (tap) controller during power up of the qt1f- plus . if boundary scan testing is to be performed and the pin is held low, then a pull-down resistor value should be chosen which will allow the tester to drive this pin high, but still meet the v il requirements listed in the "input, output and input/output parameters" section of this data sheet for worst case leakage currents of all devices sharing this pull-down resistor. figure 44. boundary scan schematic tap controller data registers instruction register tdi tdo in out boundary scan serial test data core logic of qt1f- plus boundary scan register signal input and output pins device trs tck tms control pins
- 84 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers boundary scan chain a boundary scan description language (bsdl) file for the qt1f- plus TXC-03103C device will be made available on the transwitch internet web site at www.transwitch.com. there are 141 scan cells in the qt1f- plus boundary scan chain. bidirectional device pins require two scan cells. additional scan cells are used for direction control as needed. the follow- ing table shows the listed order of the scan cells and their functions. cells that are not associated with a pin are marked "na". scan cell no. i/o pin no. symbol comments 140 control na xiotri_b a ? 1 ? enables the outputs of i/o type output3. 139 output3 39 rdata1_o39 138 output3 38 rsigl1_o38 137 control na xrxc1_b a ? 0 ? makes pins 37, 36 to be output. 136 bidir_in 37 rclk1_io37 135 bidir_out 37 rclk1_io37 134 bidir_in 36 rsync1_io36 133 bidir_out 36 rsync1_io36 132 input 35 tdata1_i35 131 control na xtft4_enb a ? 0 ? makes pin 34 to be output. 130 bidir_in 34 tsigl1_io34 129 bidir_out 34 tsigl1_io34 128 input 33 tclk1_i33 127 input 32 tsync1_i32 126 output3 31 rdata2_o31 125 output3 29 rsigl2_o29 124 control na xrxc2_b a ? 0 ? makes pins 28, 27 to be output. 123 bidir_in 28 rclk2_io28 122 bidir_out 28 rclk2_io28 121 bidir_in 27 rsync2_io27 120 bidir_out 27 rsync2_io27 119 input 26 tdata2_i26 118 control na xtft2_enb a ? 0 ? makes pin 24 to be output. 117 bidir_in 24 tsigl2_io24 116 bidir_out 24 tsigl2_io24 115 input 23 tclk2_i23 114 input 22 tsync2_i22 113 output3 21 rdata3_o21 112 output3 19 rsigl3_o19
- 85 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 111 control na xrxc3_b a ? 0 ? makes pins 18, 17 to be output. 110 bidir_in 18 rclk3_io18 109 bidir_out 18 rclk3_io18 108 bidir_in 17 rsync3_io17 107 bidir_out 17 rsync3_io17 106 input 16 tdata3_i16 105 control na xtft3_enb a ? 0 ? makes pin 15 to be output. 104 bidir_in 15 tsigl3_io15 103 bidir_out 15 tsigl3_io15 102 input 13 tclk3_i13 101 input 12 tsync3_i12 100 output3 11 rdata4_o11 99 output3 10 rsigl4_o10 98 control na xrdy_enb a ? 0 ? makes pin 9 to be output. a ? 1 ? makes pin 9 to be tristate. 97 output3 9 rdy_o9 96 control na xrxc4_b a ? 0 ? makes pins 8, 7 to be output. 95 bidir_in 8 rclk4_io8 94 bidir_out 8 rclk4_io8 93 bidir_in 7 rsync4_io7 92 bidir_out 7 rsync4_io7 91 input 6 tdata4_i6 90 control na xtft4_enb a ? 0 ? makes pin 5 to be output. 89 bidir_in 5 tsigl4_io5 88 bidir_out 5 tsigl4_io5 87 input 4 tclk4_i4 86 input 3 tsync4_i3 85 control na xref_clk_en2_b a ? 0 ? makes pin 2 to be output enabled. 84 output3 2 clkref2_o2 83 input 1 reset_l_i1 82 input 128 wr_l_i128 81 input 127 sel_l_i127 80 input 126 rd_l_i126 79 output3 125 int_o125 scan cell no. i/o pin no. symbol comments
- 86 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 78 control na xdt_en a ? 0 ? makes pins 123-114 to be output. 77 bidir_in 123 dat7_io123 76 bidir_out 123 dat7_io123 75 bidir_in 122 dat6_io122 74 bidir_out 122 dat6_io122 73 bidir_in 120 dat5_io120 72 bidir_out 120 dat5_io120 71 bidir_in 119 dat4_io119 70 bidir_out 119 dat4_io119 69 bidir_in 118 dat3_io118 68 bidir_out 118 dat3_io118 67 bidir_in 117 dat2_io117 66 bidir_out 117 dat2_io117 65 bidir_in 115 dat1_io115 64 bidir_out 115 dat1_io115 63 bidir_in 114 dat0_io114 62 bidir_out 114 dat0_io114 61 input 113 addr11_i113 60 input 112 addr10_i112 59 input 110 addr9_i110 58 input 109 addr8_i109 57 input 108 addr7_i108 56 input 107 addr6_i107 55 input 106 addr5_i106 54 input 105 addr4_i105 53 input 104 addr3_i104 52 input 103 addr2_i103 51 input 102 addr1_i102 50 input 101 addr0_i101 49 input 100 sysclk_i100 48 input 99 moto_i99 47 output3 98 lcs4_l_o98 46 output3 97 ltclk4_o97 45 output3 96 tneg4_o96 scan cell no. i/o pin no. symbol comments
- 87 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 44 output3 95 tpos4_o95 43 input 93 lrclk4_i93 42 input 92 rneg4_i92 41 input 91 rpos4_i91 40 input 90 lint4_i90 39 output3 88 lcs3_l_o88 38 output3 87 ltclk3_o87 37 output3 86 tneg3_o86 36 output3 85 tpos3_o85 35 input 83 lrclk3_i83 34 input 82 rneg3_i82 33 input 81 rpos3_i81 32 input 80 lint3_i80 31 output3 79 lcs2_l_o79 30 output3 77 ltclk2_o77 29 output3 76 tneg2_o76 28 output3 75 tpos2_o75 27 input 74 lrclk2_i74 26 input 72 rneg2_i72 25 input 71 rpos2_i71 24 input 70 lint2_i70 23 output3 69 lcs1_l_o69 22 output3 68 ltclk1_o68 21 output3 67 tneg1_o67 20 output3 66 tpos1_o66 19 input 65 lrclk1_i65 18 input 64 rneg1_i64 17 input 63 rpos1_i63 16 input 62 lint1_i62 15 control na xmon_enb a ? 0 ? enables pins 61, 60. 14 output3 61 lsclk_o61 13 output3 60 lsdo_o60 12 control na xfrm_enb a ? 0 ? makes pin 59 to be output. 11 bidir_in 59 lsdi_io59 scan cell no. i/o pin no. symbol comments
- 88 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers reset procedure after power-up the qt1f- plus requires a hardware reset. this reset will reset all the per channel registers in the memory map below address x40h. it will also reset all of the global registers at addresses 004h through 0ffh. a low placed on the reset pin for at least 10 cycles of sysclk after all clocks become stable will accomplish the hardware reset. a global software reset is also available and should be applied at least 40 ms after power-up. this resets the performance counters, internal state machines, and the latched/shadow registers; it does not change the state of any of the control reg- isters. writing a 91h to control byte reset in register 005h places the qt1f- plus in a reset state. writing a value other than 91h to control byte reset will take the qt1f- plus out of the reset state. the reset register can be read to deter- mine the reset state of the qt1f- plus . a value of 01h in the reset register indicates the qt1f- plus is in a reset state; a value of 00h indicates the qt1f- plus is not in reset. a per channel version of this function is available by writing a 1 to control bit srst (bit 7) in register x05h followed by writing a 0 to control bit srst. note that all the memory locations at addresses x40h through xffh are located in a per channel internal ram and are not reset by either a hardware reset or a software reset. changing the mode of operation of a framer should be followed by a per channel software reset (srst). the mode bits can be found in framer per channel registers x00h through x04h (rail, be, enzc, ensais, ensyel, lie, lpol, txcp, rxcp, txnrzp, rxnrzp, pwrd, fdat, fpol, bfdl, txc1, txc0, rxc, tse, rse, typ1, typ0, enais, enoof, enlos, oof1, oof0, alt, syc1, syc0, fmd1 and fmd0). not resetting the framer after changing most mode control bits will have minimal effect. however, if control bits fmd1 and fmd0 (bits 2 and 1) in register x04 are changed a per channel software reset procedure is required. also, control bits located in per channel internal ram (at addresses x40h through xffh) need to be re-programmed after a change to fmd1 or fmd0. if all four framer channels of the qt1f- plus are not implemented in an application, the channels that are not used should be powered down (by setting control bit pwrd, bit 4 in register x01h to a 0) and all interrupts masked (by setting register x09h to ffh). 10 bidir_out 59 lsdi_io59 9 input 51 scan_enb 8 input 50 iotri_l_i50 7 input 49 cso_l_i49 6 output3 48 prbsool_o48 5 control na xref_clk_en1_b a ? 0 ? makes pin 46 to be output enabled. 4 output3 46 clkref1_o46 3 input 43 config1_i43 2 input 42 config2_i42 1 input 41 lo_i41 0 input 40 t1si_i40 scan cell no. i/o pin no. symbol comments
- 89 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers memory map the qt1f- plus memory map contains registers and counters which may be accessed by the microprocessor. addresses which are shown as spare, or which are not listed in the memory map, must not be accessed by the microprocessor. the status designation r indicates a read-only unlatched register location, r(l) a read-only latched register location, w a write-only register location and rw a read/write register location. r and r(l) register bit positions designated as reserved (r) will read out an indeterminate value unless a 0 or 1 read value is indicated. some rw reserved (r) bit positions do not exist (i.e., they have no memory associated with them), so that any values written to these bits cannot be read. those that do have associated memory should be written to 0, as indicated in the following tables. rw reserved (r) bit positions should not be used for storage of any application information. device id registers customer notebook register global software register global configuration registers address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000r11010111 001r11110000 002r11000001 003r00000000 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 004 rw user defined register address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 005 rw qt1f- plus software reset (reset byte) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 006 rw gim rise fall ipol enpmfm r (0) r (0) enhwm 007 spare 008 spare 009 spare 01a-0fe spare 0ff rw reserved (set to 0) ends0lb reserved r (0)
- 90 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers global status indication, interrupt mask and pointer registers line interface control and monitoring registers loop-up/down control registers transmit and receive sync delay registers clock reference selection register address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00a r glos gais goof gyel gcfa/ gaisci qsef gtxslip grxslip 00b rw gmlos gmais gmoof gmyel gmcfa/ gmaisci gmsef gmtxslip gmrxslip 00c r reserved cha4 cha3 cha2 cha1 00d spare 00e r reserved chdl4 chdl3 chdl2 chdl1 00f spare address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 010 rw lcb7 - lcb0 (command byte) 011 rw ldo7 - ldo0 (line interface data output) 012 r ldi7 - ldi0 (line interface data input) 013 rw bdcst prbsfr prbsen esp/ emon rxtx enmonfr t1chcs1 t1chcs0 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 014 rw r (0) lu6-lu0 (loop-up code) 015 rw r (0) ld6-ld0 (loop-down code) 016 rw reserved ulen1 ulen0 r (0) dlen1 dlen0 address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 017 rw tsd7 - tsd0 (transmit sync delay) 018 rw rsd7 - rsd0 (receive sync delay) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 019 rw cr2s1 cr2s0 enref2 1544khz enref1 r cr1s1 cr1s0
- 91 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers per channel control and status indication registers the following registers configure, control or provide status information on a per channel basis. when an address location is written as xxxh, the first x indicates 1, 2, 3 or 4 to identify the associated channel, which corresponds to the like-num- bered framer (n=1, 2, 3 or 4). framer configuration and control registers software reset and loopback control register system ais and test registers address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 100 200 300 400 rw rail be enzc ensyel fod ensais lie lpol 101 201 301 401 rw txcp rxcp txnrzp pwrd fdat fpol bfdl rxnrzp 102 202 302 402 rw txc1 txc0 rxc tse rse tsr rsr ft1m 103 203 303 403 rw typ1 typ0 rxf txf ose enais enoof enlos 104 204 304 404 rw oof1 oof0 alt syc1 syc0 fmd1 fmd0 rsyc 13a 23a 33a 43a rw rfd8 rfd7 rfd6 rfd5 rfd4 rfd3 rfd2 rfd1 13b 23b 33b 43b rw rfd16 rfd15 rfd14 rfd13 rfd12 rfd11 rfd10 rfd9 13c 23c 33c 43c rw rfd24 rfd23 rfd22 rfd21 rfd20 rfd19 rfd18 rfd17 13d 23d 33d 43d rw tfd8 tfd7 tfd6 tfd5 tfd4 tfd3 tfd2 tfd1 13e 23e 33e 43e rw tfd16 tfd15 tfd14 tfd13 tfd12 tfd11 tfd10 tfd9 13f 23f 33f 43f rw tfd24 tfd23 tfd22 tfd21 tfd20 tfd19 tfd18 tfd17 address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 105 205 305 405 rw srst alup txup txdn payl tx1s rlp llp address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 106 206 306 406 rw r (0) r r r (0) insprbs sfz rxfs txfs 107 207 307 407 rw r svtais sysall1 crc frme yel aise bpv
- 92 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers ds1 status and mask registers counters and counter shadow registers address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 109 209 309 409 rw mlos mais moof myel mcfa/ maisci msef mtxslip mrxslip 110 210 310 410 r los ais oof yel cfa/aisci sef txslip rxslip 111 211 311 411 rw llos lais loof lyel lcfa/ laisci lsef ltxslip lrxslip 112 212 312 412 rw plos pais poof pyel pcfa/ pa i s c i psef ptxslip prxslip 113 213 313 413 rw flos fais foof fyel fcfa/ fa i s c i fsef ftxslip frxslip address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1ec 2ec 3ec 4ec r reserved 1ed 2ed 3ed 4ed r reserved 1ee 2ee 3ee 4ee r reserved 1ef 2ef 3ef 4ef r reserved 1f0 2f0 3f0 4f0 rw lcrc7 - lcrc0 (latched crc-6 error counter shadow register, 9 bits) 1f1 2f1 3f1 4f1 rw lcrco reserved (set to 0) lcrc8 1f2 2f2 3f2 4f2 rw crc7 - crc0 (crc-6 error counter, 9 bits) 1f3 2f3 3f3 4f3 rw crco reserved (set to 0) crc8 1f4 2f4 3f4 4f4 rw lcv7 - lcv0 (latched coding violation counter shadow register, 16 bits) 1f5 2f5 3f5 4f5 rw lcv15 - lcv8 (latched coding violation counter shadow register, 16 bits) 1f6 2f6 3f6 4f6 rw lcvo reserved (set to 0) 1f7 2f7 3f7 4f7 rw cv7 - cv0 (coding violation counter, 16 bits) 1f8 2f8 3f8 4f8 rw cv15 - cv8 (coding violation counter, 16 bits) 1f9 2f9 3f9 4f9 rw cvo reserved 1fa 2fa 3fa 4fa rw lfbe7 - lfbe0 (latched framing bit error counter shadow register, 8 bits) 1fb 2fb 3fb 4fb rw lfbeo reserved (set to 0) 1fc 2fc 3fc 4fc rw fbe7 - fbe0 (framing bit error counter, 8 bits) 1fd 2fd 3fd 4fd rw fbeo reserved (set to 0) 1fe 2fe 3fe 4fe r reserved 1ff 2ff 3ff 4ff r reserved
- 93 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers operational status registers slip buffer pointer status registers receive time slot control registers address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 114 214 314 414 r txs1 txs0 rxs1 rxs0 vtais vtrdi reserved 115 215 315 415 r rxsf txsf reserved up down lint 11b 21b 31b 41b r reserved address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 120 220 320 420 r twp7 - twp0 (transmit slip buffer write pointer) 121 221 321 421 r trp7 - trp0 (transmit slip buffer read pointer) 122 222 322 422 r twsbs reserved twpf4 - twpf0 (tx write pointer frame) 123 223 323 423 r trsbs reserved trpf4 - trpf0 (tx read pointer frame) 124 224 324 424 r rwp7 - rwp0 (receive slip buffer write pointer) 125 225 325 425 r rrp7 - rrp0 (receive slip buffer read pointer) 126 226 326 426 r rwsbs reserved rwpf4 - rwpf0 (rx write pointer frame) 127 227 327 427 r rrsbs reserved rrpf4 - rrpf0 (rx read pointer frame) 128 228 328 428 r reserved 129 229 329 429 r reserved address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 12a 22a 32a 42a r reserved 12b 22b 32b 42b r reserved 1e0 2e0 3e0 4e0 rw rde8 - rde1 (rx time slots 8-1 selection) 1e1 2e1 3e1 4e1 rw rde16 - rde9 (rx time slots 16-9 selection) 1e2 2e2 3e2 4e2 rw rde24 - rde17 (rx time slots 24-17 selection) 1e3 2e3 3e3 4e3 r reserved
- 94 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers receive time slot registers transmit time slot control registers transmit time slot registers signaling control registers address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 140 - 157 ch 1 240 - 257 ch 2 340 - 357 ch 3 440 - 457 ch 4 rw frame 1 rds0 (1) - rds0 (24) receive time slots ts1 - ts24 x40 - time slot 1 x57 - time slot 24 158 - 16f ch 1 258 - 26f ch 2 358 - 36f ch 3 458 - 46f ch 4 rw frame 2 rds0 (1) - rds0 (24) receive time slots ts1 - ts24 x58 - time slot 1 x6f - time slot 24 address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 12c 22c 32c 42c r reserved 12d 22d 32d 42d r reserved 12e 22e 32e 42e r reserved 12f 22f 32f 42f r reserved 1e4 2e4 3e4 4e4 rw tde8 - tde1 (tx time slots 8-1 selection) 1e5 2e5 3e5 4e5 rw tde16 - tde9 (tx time slots 16-9 selection) 1e6 2e6 3e6 4e6 rw tde24 - tde17 (tx time slots 24-17 selection) 1e7 2e7 3e7 4e7 r reserved address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 190 - 1a7 ch 1 290 - 2a7 ch 2 390 - 3a7 ch 3 490 - 4a7 ch 4 rw frame 1 tds0 (1) - tds0 (24) transmit time slots ts1 - ts24 x90 - time slot 1 xa7 - time slot 24 1a8 - 1bf ch 1 2a8 - 2bf ch 2 3a8 - 3bf ch 3 4a8 - 4bf ch 4 rw frame 2 tds0 (1) - tds0 (24) transmit time slots ts1 - ts24 xa8 - time slot 1 xbf - time slot 24 address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1e8 2e8 3e8 4e8 rw se8 - se1 (signaling enable for channels 8-1 selection) 1e9 2e9 3e9 4e9 rw se16 - se9 (signaling enable for channels 16-9 selection) 1ea 2ea 3ea 4ea rw se24 - se17 (signaling enable for channels 24-17 selection) 1eb 2eb 3eb 4eb r reserved
- 95 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers receive and transmit signaling registers address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 180 280 380 480 rw receive signaling bits a8-a1 181 281 381 481 rw receive signaling bits a16-a9 182 282 382 482 rw receive signaling bits a24-a17 183 283 383 483 r reserved 184 284 384 484 rw receive signaling bits b8-b1 185 285 385 485 rw receive signaling bits b16-b9 186 286 386 486 rw receive signaling bits b24-b17 187 287 387 487 r reserved 188 288 388 488 rw receive signaling bits c8-c1 189 289 389 489 rw receive signaling bits c16-c9 18a 28a 38a 48a rw receive signaling bits c24-c17 18b 28b 38b 48b r reserved 18c 28c 38c 48c rw receive signaling bits d8-d1 18d 28d 38d 48d rw receive signaling bits d16-d9 18e 28e 38e 48e rw receive signaling bits d24-d17 18f 28f 38f 48f r reserved 1d0 2d0 3d0 4d0 rw transmit signaling bits a8-a1 1d1 2d1 3d1 4d1 rw transmit signaling bits a16-a9 1d2 2d2 3d2 4d2 rw transmit signaling bits a24-a17 1d3 2d3 3d3 4d3 r reserved 1d4 2d4 3d4 4d4 rw transmit signaling bits b8-b1 1d5 2d5 3d5 4d5 rw transmit signaling bits b16-b9 1d6 2d6 3d6 4d6 rw transmit signaling bits b24-b17 1d7 2d7 3d7 4d7 r reserved 1d8 2d8 3d8 4d8 rw transmit signaling bits c8-c1 1d9 2d9 3d9 4d9 rw transmit signaling bits c16-c9 1da 2da 3da 4da rw transmit signaling bits c24-c17 1db 2db 3db 4db r reserved 1dc 2dc 3dc 4dc rw transmit signaling bits d8-d1 1dd 2dd 3dd 4dd rw transmit signaling bits d16-d9 1de 2de 3de 4de rw transmit signaling bits d24-d17 1df 2df 3df 4df r reserved
- 96 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers receive frame bit registers hdlc link control registers hdlc link transmit and receive data registers hdlc link status registers ds0 loopback control registers address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 130 230 330 430 rw fe2/fs4 di/ft4 crc2/fs3 di/ft3 fe1/fs2 di/ft2 crc1/fs1 di/ft1 131 231 331 431 rw fe4/x di/x crc4/x di/x fe3/fs6 di/ft6 crc3/fs5 di/ft5 132 232 332 432 rw fe6/x di/x crc6/x di/x fe5/x di/x crc5/x di/x 133 233 333 433 rw fe2/fs4 di/ft4 crc2/fs3 di/ft3 fe1/fs2 di/ft2 crc1/fs1 di/ft1 134 234 334 434 rw fe4/x di/x crc4/x di/x fe3/fs6 di/ft6 crc3/fs5 di/ft5 135 235 335 435 rw fe6/x di/x crc6/x di/x fe5/x di/x crc5/x di/x address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 108 208 308 408 rw ehr eht tab eom rhie thie ebri ebt 10c 20c 30c 40c r reserved address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10a 20a 30a 40a w hdlc transmit data thd7 - thd0 10b 20b 30b 40b rw reserved transmit bit code data tbcd5 - tbcd0 117 217 317 417 r hdlc receive data rhd7 - rhd0 118 218 318 418 r reserved c4 - c0 (hdlc receive fifo depth) 119 219 319 419 r reserved receive bit code data rbcd5 - rbcd0 address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10e 20e 30e 40e rw erhis2 - erhis0 ethis erxfs1 - erxfs0 etxfs1 - etxfs0 10f 20f 30f 40f rw mrhis2 - mrhis0 mthis mrxfs1 - mrxfs0 mtxfs1 - mtxfs0 116 216 316 416 r rhis2 - rhis0 this rxfs1 - rxfs0 txfs1 - txfs0 address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 11c 21c 31c 41c rw lbd8 lbd7 lbd6 lbd5 lbd4 lbd3 lbd2 lbd1 11d 21d 31d 41d rw lbd16 lbd15 lbd14 lbd13 lbd12 lbd11 lbd10 lbd9 11e 21e 31e 41e rw lbd24 lbd23 lbd22 lbd21 lbd20 lbd19 lbd18 lbd17
- 97 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers spare registers the following registers are designated as spare, where x = 1, 2, 3 or 4. these registers must not be accessed for read or write operations by the microprocessor: 007h, 008h, 009h, 00dh, 00fh, 01ah to 0feh, x1ah, x1fh reserved and test registers the following bit locations in read/write registers are designated as reserved and require zeros to be written into them as indicated in the first two tables below. some of these bits are designated as internal test bits, etc. the per framer test reg- isters x38 and x39 in the third table may be read but must not be written during normal operation. global registers per framer registers (x = 1, 2, 3, 4) per framer test registers (x = 1, 2, 3, 4) register bits comments 006 2 - 1 write a 0 to these bit locations 014 7 write a 0 to this bit location 015 7 write a 0 to this bit location 016 2 write a 0 to this bit location 0ff 7 - 5 write a 0 to these bit locations 0ff 0 write a 0 to this bit location register bits comments x06 7, 4 write a 0 to these bit locations xf1 6 - 1 write a 0 to these bit locations xf3 6 - 1 write a 0 to these bit locations xf6 6 - 0 write a 0 to these bit locations xfb 6 - 0 write a 0 to these bit locations xfd 6 - 0 write a 0 to these bit locations register bits comments x38 7 - 0 lower byte sf loopback code counter x39 7 - 0 upper byte sf loopback code counter
- 98 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers memory map descriptions global registers device id registers the manufacturer id, part number code and version of the qt1f- plus are implemented in registers 000h - 003h with read-only capability, as shown in the memory map section above. the manufacturer id is 107 (decimal), and has been assigned for transwitch by the joint electron device engineering council (jedec) of the solid state products engineer- ing council. this field is 11 bits in length, and is assigned to bits 3 through 0 in register 001h, and bits 7 through 1 in reg is- ter 000h. bit 0 (lsb) in register 000h is fixed as a 1, so the value stored in the entire 12- bit field is 0d7h. the part number field is 16 bits long. the part number code used here for the qt1f- plus is 03103 (decimal). the binary equivalent of 03103 (decimal) is assigned to bits 3-0 in register 003h, bits 7-0 in register 002h, and bits 7-4 (lsb) in register 001h (0c1fh). the revision level field at bits 7-4 in register 003h represents the version number of the device and is set to 0h, but this value may be changed as the device evolves. customer notebook register the read/write bits in this register location are provided for use by the customer ? s application software. global software register the control bits in this read/write register location are used for resetting the qt1f- plus . address bit symbol description 004 7-0 notebook user defined register: the bits in this read/write register are provided for use by the application software. the contents of this read/write register will have no direct effect on the operation of the qt1f- plus . address bit symbol description 005 7-0 reset software reset: writing a 91h into this location will reset the qt1f- plus . writing a value other than 91h will remove the qt1f- plus from the reset state. reading this location provides a value of 00h if the qt1f- plus is not in reset, and 01h if the qt1f- plus is reset. the qt1f- plus defaults to reset deactivation on an external hardware reset (e.g., power-up). at least 40 ms after power-up, a software reset should be applied to this register location in order to clear the qt1f- plus prior to programming the register positions. the software reset resets the performance counters, internal state machines, and the latched/shadow registers. the control registers are not affected by this reset. in addition to this global reset byte, each of the four framers has an individual software reset bit, which is assigned to bit 7 (srst) in register location x05h (where x corresponds to the framer ? s num- ber, n).
- 99 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers global configuration registers the bits in these read/write registers control qt1f- plus operations on a global basis for all four framers. address bit symbol description 006 7 gim global interrupt mask bit: a 1 disables (masks) the hardware interrupt pin (pin 125). when not masked (0), any latched status event (if not masked by the corresponding event mask bit) causes a hardware interrupt to occur. 6rise rising edge latched status event bits enable: this bit works in con- junction with the fall control bit (bit 5) to provide the following states for controlling the setting of the latched status event indication bits for the four framers. rise fa l l action 0 0 latched status bit indications for all framers dis- abled. hardware interrupt indication disabled. 0 1 latched status indication bits for all framers set on a negative status event bit indication transition. 1 0 latched status indication bits for all framers set on a positive status event bit indication transition. 1 1 latched status indication bits for all framers set on both a positive and a negative status event bit indi- cation transition. 5fall falling edge latched status event bits enable: works in conjunction with the rise control bit according to the table given above. 4ipol hardware interrupt polarity sense: when set to 1, the polarity of the hard- ware interrupt pin (pin 125) is inverted from active high to active low for the intel microprocessor bus. when the motorola microprocessor bus is selected, the polarity of the hardware interrupt pin (pin 125) is inverted from active low to active high. 3enpmfm enable performance monitoring and fault monitoring feature: when set to 1, the monitoring feature for the pm and fm shadow registers (x12h and x13h) is enabled and the latching of the shadowed performance counters (xf0, xf1, xf4, xf5, xf6, xfa and xfb) is enabled. the register bits set on the rising edges of the one second pulse, which must be present on the t1si pin (pin 40). when set to 0, the monitoring feature is disabled. 2-1 reserved reserved: set to 0. 0 enhwm enable hardware mask hierarchy: when set to 1, the masking hierarchy for the alarms is enabled according to the table given below: alarm suppression table (shaded columns indicate suppressed alarms) direction los line ais oof yel slips line port to system x x x
- 100 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers global status indication, mask and pointer registers these registers are read-only, except for the mask register 00bh, which is read/write. the bits in the global status indication register 00ah indicate an alarm caused by a line event on a global basis (i.e., in any framer). if the corresponding mask bit is written with a 1 in the ds1 mask register (x09h) it prevents an interrupt gen- eration, but the global indication will be present in register 00ah. each event bit is formed by or-gating the corresponding event bits in each of the four framer channels (registers x10h) to provide the individual status indication in register 00ah. a 1 written into a bit position in the global mask register 00bh will mask the inter- rupt indication for the corresponding bit position in register 00ah. the bits in register locations 00ch and 00eh provide a pointer to the framer which caused the line or hdlc link latched event. global status indication register 0ff 7-5 reserved set to zero. 4 ends0lb enable ds0 loopback feature: a 1 enables the ds0 channel loopback feature for the four framers. ds0 channel loopbacks occur when the corre- sponding control bits lbd24-lbd1 are written with a 1. clock tclkn must be present for the ds0 loopback feature to function. 3-1 reserved these bit locations do not exist. 0 reserved set to zero. address bit symbol description 00a 7 glos global loss of signal (los) indication: this bit is a 1 when any of the four framer channels has detected a loss of signal alarm. 6gais global ais indication: this bit is a 1 when any of the four framer channels has detected an ais alarm. 5goof global out of frame (oof) indication: this bit is a 1 when any of the four framer channels has detected an out of frame alarm. 4gyel global yellow alarm (yel) indication: this bit is a 1 when any of the four framers has detected a yellow alarm. 3 gcfa/gaisci global change in frame alignment (cfa)/ais-ci indication: this bit is a 1 when any of the four framer channels has detected a change in frame alignment or detected the ais-ci signature. 2 gsef global severely errored frame (sef) indication: this bit is a 1 when any of the framer channels has detected a severely errored frame (sef) alarm. 1gtxslip global transmit slip indication: this bit is a 1 when any of the four framer channels has detected a transmit slip. 0 grxslip global receive slip indication: this bit is a 1 when any of the four framer channels has detected a receive slip. address bit symbol description
- 101 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers global interrupt mask register global pointer registers address bit symbol description 00b 7 gmlos global loss of signal (los) mask bit: when set to 1, a loss of signal alarm detected in any framer channel (llos, registers x11h) is masked from provid- ing an interrupt indication. 6gmais global ais mask bit: when set to 1, an ais condition detected in any framer channel (lais, registers x11h) is masked from providing an interrupt indication. 5gmoof global out of frame (oof) mask bit: when set to 1, an out of frame alarm detected in any framer channel (loof, registers x11h) is masked from providing the global indication in register 00ah. 4gmyel global yellow alarm (yel) indication mask bit: when set to 1, a yellow alarm in any framer channel (lyel, registers x11h) is masked from provid- ing an interrupt indication. 3gmcfa/ gmaisci global change in frame alignment (cfa)/ais-ci indication mask bit: when set to 1, a change in frame alignment indication or ais-ci indication in any framer channel (lcfa/laisci, registers x11h) is masked from provid- ing an interrupt indication. 2gmsef global severely errored frame (sef) mask bit: when set to 1, a severely errored frame alarm detected in any framer channel (lsef, regis- ters x11h) is masked from providing an interrupt indication. 1gmtxslip global transmit slip indication mask bit: when set to 1, a transmit slip detected in any framer channel (ltxslip, registers x11h) is masked from providing an interrupt indication. 0 gmrxslip global receive slip indication mask bit: when set to 1, a receive slip detected in any framer channel (lrxslip, registers x11h) is masked from providing an interrupt indication. address bit symbol description 00c 7-4 r reserved: disregard these bits. 3-0 cha4-cha1 channel activity line events for channels 4-1: a 1 in a bit position points to (indicates) the framer channel that caused the global status indication because of a line event (e.g., loss of signal). for example, 0011 indicates that channels 2 and 1 have a latched line event. 00e 7-4 r reserved : disregard these bits. 3-0 chdl4-chdl1 channel activity hdlc link event for channels 4-1: a 1 in a bit position points to (indicates) the framer channel that caused the global status indica- tion because of a hdlc link event (e.g., receive fifo event). for example, 1000 indicates that channel 4 has a latched data link event.
- 102 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers line interface control and monitoring registers these registers are read/write, except for register 012h, which is read-only unlatched. the control bits in these registers determine the line interface control information flow between the qt1f- plus and the external line interface transceivers, enable the pseudo-random generator and analyzer, and enable the monitor mode for the qt1f- plus . the line interface control feature is enabled by placing a low on the config1 pin (pin 43). address bit symbol description 010 7-0 lcb7-lcb0 line interface control command byte: the bits in this register contain the command byte for the external line interface transceiver. the contents of the command byte written into this location depend on the transceiver selected. please consult the transceiver data sheet for the appropriate codes. the com- mand byte is transmitted via the line interface control serial port output (lsdo). this byte is shifted out of this register starting with bit lcb0 first, and represents the first byte transmitted on the lsdo pin (pin 60). 011 7-0 ldo7-ldo0 line interface control serial data output byte: the bits in this register con- tain the data byte which is written to the selected external line interface trans- ceiver. the data byte is transmitted via the line interface control serial port output (lsdo). this byte is shifted out of this register starting with bit ldo0 first, and represents the second byte transmitted on the lsdo pin. 012 7-0 ldi7-ldi0 line interface control serial data input byte: the bits in this register contain the data byte which is read from the selected external line interface transceiver. the data byte is received via the line interface control serial port input (lsdi). this byte is shifted into this register starting with bit ldi0 first. 013 7 bdcst broadcast command: when this bit is set to 1, the two bytes in the line inter- face control command and serial data output byte registers are broadcasted to all external line interface transceivers. this is accomplished by forcing all line interface chip select signals (lcsn ) active low. this feature is disabled in the internal ds1 monitor mode (config2 pin is high). 6prbsfr prbs framed mode : when this bit is set to 1, the internal 2 15 -1 prbs gener- ator and analyzer are configured to operate in the framed mode, which means that the channel ? s transmit framer block generates framing. when set to 0 for unframed mode, the internal 2 15 -1 prbs generator and analyzer are config- ured to operate on all of the bits in the transmit and receive data highways. 5 prbsen prbs enable: this bit is enabled in the transmission mode only. when this bit is set to 1, the internal 2 15 -1 prbs analyzer is enabled. the ds1 channel selection bits (bits 1 and 0) in this register select which channel's receive data highway is connected to the analyzer. the state of the analyzer is provided on pin prbsool. a low on this pin indicates that the analyzer is locked, while a high indicates the unlocked state. the recovered line clock is the clock source for the analyzer. if the receive slip buffer is enabled, its read clock source is the lrclkn input pin. the lo input pin is the clock source for the generator. if the transmit slip buffer is enabled, then the input lo must be synchronous and in phase with tclkn.
- 103 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 013 (cont.) 4 esp/emon enable serial port: this feature is enabled when a low is placed on the config2 pin. when set to 1, a single transfer takes place between the exter- nal line interface transceiver and its associated qt1f- plus framer via the line interface control serial port. the external transceiver is accessed by an active low chip select signal (lcsn ) for the transceiver selected by the ds1 selection bits, bits 1 and 0 in this register. this bit must be first set to 0 and then to 1 before another transfer is enabled. enable monitor port: the internal ds1 monitor mode is selected by placing a high on the config2 pin. the monitor mode has the following operating con- figurations, controlled by bits 4, 3 and 2 of this register: rxtx esp/emon enmonfr action x 0 x tristate mondto and monclk leads. 0 1 x monitor transmit framer output via the monclk and mondto leads. 1 1 0 receive framer input (nrz) signal is monitored via the monclk and mondto leads. 1 1 1 receive output framer signals are monitored via the monclk and mondto leads. in additions, the frame pulse is provided via the monfrm lead. during the loss of signal condition, an all ones signal is placed on the mondto pin and the monfrm pin will continue to send out frame pulses according to the prior framing bit position. 3rxtx rx or tx monitor selection: when the internal ds1 monitor mode is selected (a high is placed on the config2 pin), a 0 enables the transmit side to be monitored. a 1 enables the receive side to be monitored. 2enmonfr enable frame monitor: this bit operates in conjunction with the config2 pin and the rxtx and esp/emon control bits according to the table given above. 1-0 t1chcs1- t1chcs0 ds1 channel selection: selects the external line interface transceiver, the internal ds1(t1) channel (framer) for monitoring and the receive data highway channel for the internal 2 15 -1 prbs analyzer, according to the table given below: bit 1 bit 0 transceiver/ds1(t1) monitored/analyzer 0 0 channel 1 0 1 channel 2 1 0 channel 3 1 1 channel 4 address bit symbol description
- 104 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers loop up/down control registers the values written to these registers are transmitted as up or down loop codes when enabled for a channel. address bit symbol description 014 7 r reserved: set to 0. 6-0 lu6-lu0 loop-up code: the value written to this register represents a loop-up code. the number of bits in the code that are to be transmitted is determined by the value written to control bits ulen1 and ulen0 (bits 4 and 3 in regis- ter 016h). the loop-up code is transmitted continuously for a channel when control bit txup is set (bit 5 in register x05h). for csu loop-up code (10000b), this must be done with 10h at register 014h and "01" at bits 4-3 of register 016h. for ni loop-up code (11000b), this must be done with 0ch or 06h or 11h at register 014h and "01" at bits 4-3 of register 016h. do not set 18h or 03h at register 014h for this application. the value written in this register is used to control the automatic loop-up detec- tion circuit (see control bit alup, bit 6 of register x05h). 015 7 r reserved: set to 0. 6-0 ld6-ld0 loop-down code: the value written to this register represents a loop- down code. the number of bits in the code that are to be transmitted is determined by the value written to control bits dlen1 and dlen0 (bits 1 and 0 in register 016h). the loop-down code is transmitted continuously for a channel when control bit txdn is set (bit 4 in register x05h). for csu loop-down code (100100b), this must be done with 12h or 09h at register 015h and "10" at bits 1-0 of register 016h. do not set 24h at register 015h for this application. for ni loop-down code (11100b), this must be done with 0eh or 13h at register 015h and "01" at bits 1-0 of register 016h. do not set 1ch or 07h at register 015h for this application. the value written in this register is used to control the automatic loop-down detection circuit (see control bit alup, bit 6 of register x05h). 016 7-5 r reserved: these bit locations do not exist. 4-3 ulen1 ulen0 loop-up length: these two control bits set the number of loop-up bits which are transmitted by the value written into the loop-up code register (bits 6-0 in register 014h) according to the following table. ulen1 (bit 4) ulen0 (bit 3) length of the code 00 4 01 5 10 6 11 7 note: the length of the loop-up code in register 014h is right justified. the value written in this register is used to control the automatic loop-up detection circuit (see control bit alup, bit 6 register x05h). for codes of length 3 or 2 use length 6 or 4 and repeat pattern.
- 105 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers transmit and receive sync delay registers the values written in these two read/write registers control the number of clock cycles the transmit sync pulse (tsyncn) and receive system sync pulse (rsyncn) may be delayed relative to the transmit system clock (tclkn), and receive system clock (rclkn), respectively. 016 (cont.) 2r reserved: set to 0. 1-0 dlen1 dlen0 loop-down length: these two control bits set the number of loop-down bits which are transmitted by the value written into the loop-down code regis- ter (bits 6-0 in register 015h) according to the following table. dlen1 (bit 1) dlen0 (bit 0) length of the code 00 4 01 5 10 6 11 7 note: the length of the loop-down code in register 015h is right justified. the value written in this register is used to control the automatic loop-down detection circuit (see control bit alup, bit 6 register x05h). for codes of length 3 or 2 use length 6 or 4 and repeat pattern. address bit symbol description 017 7-0 tsd7-tsd0 transmit sync delay: the value written into this register location specifies the number of transmit clock cycles (tclkn) that the transmit sync signal (tsyncn) is delayed internal to the qt1f- plus , in increments of one bit time. the default value is 00 hex. 018 7-0 rsd7-rsd0 receive sync delay: the value written into this register location specifies the number of receive clock cycles (rclkn) that the receive sync signal (rsyncn) is delayed internal to the qt1f- plus , in increments of one bit time. the default value is 00 hex. this function is only available when rclkn and rsyncn are inputs (control bit rxc is set to 0). address bit symbol description
- 106 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers clock reference selection register the control bits in this read/write register are used to control the clock references for the qt1f- plus . address bit symbol description 019 7-6 cr2s1- cr2s0 reference channel clock 2 selection: selects the channel from which the reference clock clkref2 (pin 2) is derived, according to the table given below: bit 7 bit 6 reference clock derived from 0 0 channel 1 0 1 channel 2 1 0 channel 3 1 1 channel 4 5 enref2 enable reference clock 2: when set to 1, the reference clock on clkref2 (pin 2) is enabled. the reference clock is selected by the refer- ence channel clock 2 selection control bits (bits 7 and 6), and is derived from receive clock (lrclkn) for the selected channel. when set to 0, clkref2 (pin 2) is tristated. please note that when set to 1, clkref2 will be forced low when a loss of signal (los) is detected either locally or from the external line interface transceiver when control bit lie in bit 1 of framer configuration register x00h is a 1. 4 1544khz 1544 khz reference clock enable: when set to 1, the 1544 khz reference clock selected by the reference channel clock 1 or 2 selection control bits is provided on the pins clkref1 and/or clkref2, if enabled by control bits enref1, 2 in this register. when set to 0, a divide by 193 circuit is placed between the receive line clock (lrclkn) and pins clkref1 and/or clkref2 so that 8 khz reference signals are provided instead of 1544khz if enabled by control bits enref1, 2 in this register. 3 enref1 enable reference clock 1: when set to 1, the reference clock on clkref1 (pin 46) is enabled. the reference clock is selected by the refer- ence channel clock 1 selection control bits (bits 1 and 0), and is derived from receive clock (lrclkn) for the selected channel. when set to 0, clkref1 (pin 46) is tristated. please note that when set to 1, clkref1 will be forced low when a loss of signal (los) is detected either locally or from the external line interface transceiver when control bit lie in bit 1 of framer configuration register x00h is a 1. 2r reserved: this bit location does not exist. 1-0 cr1s1- cr1s0 reference channel clock 1 selection: selects the channel from which the reference clock clkref1 (pin 46) is derived, according to the table given below: bit 1 bit 0 reference clock derived from 0 0 channel 1 0 1 channel 2 1 0 channel 3 1 1 channel 4
- 107 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers per channel registers framer configuration and control registers the control bits in the following read/write registers are used to configure the qt1f- plus for the various modes of opera- tion on a per channel basis. in the following table, n indicates the channel (framer) number 1-4. address bit symbol description 100 - ch 1 200 - ch 2 300 - ch 3 400 - ch 4 7rail dual unipolar/nrz mode selection: when set to 1, the line interface for chan- nel n is configured to operate in the dual unipolar mode (rail interface). when set to 0, the line interface for channel n is configured to operate in the nrz mode. 6be b8zs enable: when set to 1 in the dual unipolar mode, the b8zs codec is enabled. when set to 0, the interface codec is configured for ami. in the nrz mode, the state of this bit sets the tmoden output bit value (e.g., to enable an external b8zs codec) when the fast sync feature is not selected. 5enzc enable excess zeros count: when set to 1, the bpv counter will also count excess zeros. for a b8zs line coding, 8 or more consecutive zeros will be counted as a single error, while for the ami line code, 16 or more consecutive zeros will be counted as a single error. 4 ensyel enable signaling highway yellow alarm: enabled in the transmission mode. when set to 1, a yellow alarm in the transmit signaling highway (tsigln) causes the yellow alarm to be propagated to the line for channel n. 3fod force ones density: when set to 1 with ami line coding selected (bit 6 in this register set to 0), a 1 causes a ds0 channel in the frame that contains all zeros to be transmitted with bit 7 changed to 1. 2 ensais enable signaling highway ais: enabled in the transmission mode. when set to 1, an ais alarm detected in the transmit signaling highway (tsigln) causes the ais condition to be propagated to the line for channel n. 1lie general purpose interrupt input port (lint) enable: when set to 1, the active true state present on the general purpose interrupt input port (lintn pin) is logically or-gated with the internal los signal to form the los event and interrupt for channel n. control bit lpol (bit 0 in this register) determines the active true sense. an active true signal also causes the clock reference pins clkref1 (pin 46) and/or clkref2 (pin 2), when enabled, to be held low. 0lpol general purpose interrupt input port (lint) polarity selection: when set to 1, a low present on the general purpose interrupt input port for channel n (lintn pin) is the active true state. when set to 0, a high present on the general purpose interrupt input port is the active true state.
- 108 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 101 - ch 1 201 - ch 2 301 - ch 3 401 - ch 4 7txcp transmit clock polarity selection: when set to 1, data for channel n is clocked out to the line on the rising edges of the transmit clock (ltclkn). when set to 0, data is clocked out on the falling edges of the transmit clock (ltclkn). 6rxcp receive clock polarity selection: when set to 1, data for channel n is clocked in from the line on the rising edges of the receive clock (lrclkn). when set to 0, data is clocked in on the falling edges of the receive clock (lrclkn). 5txnrzp transmit nrz data polarity selection: when set to 1, the polarity of the transmit nrz data for channel n (tldatn) is inverted. 4pwrd power-down selection: when reset to 0, the channel enters the inactivated low power state in both the transmit and receive directions. the transmit data value is determined by control bit fpol when forcing is enabled by control bit fdat. please note that control bit fdat must be set to 1 in the power-down mode, otherwise the transmit data output state will be indeterminate. 3fdat force transmit data power-down mode: this bit must be set to 0 for normal operation. when set to a 1, the transmit data is forced to the state specified by control bit fpol. this bit must be set to 1 in the power-down mode. 2fpol force transmit data polarity power-down mode: this control bit is enabled when the fdat control bit is set to 1. when set to 1, transmit data output for channel n is set to 1 (ais) in the power-down mode. when set to 0, transmit data is set to 0 in the power-down mode. please note that the forcing function occurs prior to the selected line encoding function. the following table is a summary of the actions taken by control bits pwrd, fdat and fpol. pwrd fdat fpol action 1 0 x normal operation 1 1 0 power-up with transmit data set to 0 1 1 1 power-up with transmit data set to 1 0 0 x power-down with indeterminate transmit data (do not use) 0 1 0 power-down, with transmit data set to 0 0 1 1 power-down, with transmit data set to 1 1bfdl bypass hdlc link bits: enabled in the transmission mode. when set to 1, the fdl bits in the esf format from the signaling highway (tsigln) are used in place of the hdlc data link in the transmit direction. when the sf format is selected, a 1 enables the fs bit from the signaling highway to transmitted. 0 rxnrzp receive nrz data polarity selection: when set to 1, the polarity of the received nrz data for channel n (rldatn) is inverted. address bit symbol description
- 109 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 102 - ch 1 202 - ch 2 302 - ch 3 402 - ch 4 7-6 txc1-txc0 transmit clock selection: these two bits select the clock source for clocking out data from the transmit slip buffer to the line interface according to the following table: txc1 txc0 transmit clock source 0 0 local oscillator (lo) 0 1 system transmit clock (tclkn) -transmission mode* 1 0 recovered receive clock (lrclkn) 1 1 invalid combination (do not use) * txc1, txc0 = 01 is not a valid selection in mvip mode as tclkn is 2048 khz and the required transmit line clock is 1544 khz. 5rxc receive clock select: this bit works in conjunction with control bit rse for select- ing the clock (and sync) source for shifting data out of the receive slip buffer to the system. see bit 3 below. 4 tse transmit slip buffer enable: when set to 1, the transmit slip buffer is enabled. when set to 0, the transmit slip buffer is disabled, and data bypasses the slip buffer.the transmit slip buffer must be enabled in the mvip mode. 3rse receive slip buffer enable: this bit works in conjunction with the rxc bit for enabling and disabling the receive slip buffer according to the following table. the receive slip buffer must be enabled in the mvip mode. rxc rse receive clock source/slip buffer/clock and sync 0 0 system receive clock (rclkn) and sync pulse (rsyncn); slip buffer disabled. rsyncn and rclkn are inputs. mode not recommended. 0 1 system receive clock (rclkn) and sync pulse (rsyncn); slip buffer enabled. rsyncn and rclkn are inputs. only valid mode for mvip. 1 0 recovered receive clock (lrclkn) and internal sync pulse; slip buffer disabled. rsyncn and rclkn are outputs. 1 1 recovered receive clock (lrclkn) and internal sync pulse; slip buffer enabled. rsyncn and rclkn are outputs 2tsr transmit slip buffer recenter: when set to 1, this bit forces the transmit slip buffer to recenter. afterwards this bit should be written with a 0. while set to 0, the transmit slip buffer will recenter automatically to avoid the loss of data (programmed slip). 1rsr receive slip buffer recenter: when set to 1, this bit forces the receive slip buffer to recenter. afterwards this bit should be written with a 0. while set to 0, the receive slip buffer will recenter automatically to avoid the loss of data (pro- grammed slip). 0ft1m fractional t1 mode: a 1 written to this bit position enables the transmit and receive fractional t1 feature for the channel (n, x = 1, 2, 3 or 4). a gapped clock for the ds0 channel(s) selected is provided on the rft1gcn and tft1gcn leads. ds0 channels are selected by writing a 1 to or more control bits rfd1- rfd24 (x3ah-x3ch). transmit ds0 channels are selected by writing a 1 to one or more control bits tfd1-tfd24 (x3dh-x3fh). a 0 written to this bit posi- tion, combined with a 1 in one or more of rfdc/tfdc, inverts the ds0c(s) . address bit symbol description
- 110 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 103 - ch 1 203 - ch 2 303 - ch 3 403 - ch 4 7-6 typ1-typ0 signaling type selection: the following table lists the signaling selection formats in the transmit and receive directions that are controlled by bits typ1 and typ0. typ1 typ0 signaling type 0 0 clear channel: no signaling. 0 1 two-state signaling: a bits in frames 6 and 12 for the sf for- mat, and frames 6, 12, 18 and 24 for the esf format. 1 0 four-state signaling: a bits in frame 6 for the sf format, and frames 6 and 18 for the esf format. b bits in frame 12 for sf format and frames 12 and 24 for the esf format. 1 1 sixteen-state signaling: esf format only, a bits in frame 6, b bits in frame 12, c bits in frame 18 and d bits in frame 24. 1 1 nine-state signaling: sf format only, a bits - frame 6 b bits - frame 12 c bits - frame 6 d bits - frame 12 5rxf receive signaling freeze: when set to one, received signaling bits from the ds1 line will not be written into the signaling buffer. the current contents of the signaling buffer will be used for the receive data path to the system. 4 txf transmit signaling freeze: when set to one, transmit signaling bits from the system will not be written into the signaling buffer. the current contents of the signaling buffer will be used for the transmit data path to the ds1 line interface port. 3ose ones stuffing enable: when set to 1, the received signaling bit (bit 8) in the 24 ds0 channels is forced to 1 when the signaling bit is extracted. when set to 0, the received signaling bit will remain unchanged toward the system. 2enais enable ais: when set to 1, detection of a line ais causes the a-bits in the receive signaling highway rsigln to be set to 1 in the transmission mode. the a-bits are present in time slots 3 through 24 in the signaling highway format. when enais=1, ais will also be inserted on the receive data highway when control bit svtais (bit 6) in register x07h is a 1. 1enoof enable oof: when set to 1, detection of an out of frame alarm will cause the a-bits in the receive signal highway bit rsigln to be set to 1 in the transmis- sion mode. the a-bits are present in time slots 3 through 24 in the signaling highway format. when enoof=1, ais will also be inserted on the receive data highway when control bit svtais (bit 6) in register x07h is a 1. 0 enlos enable los: when set to 1, detection of a loss of signal will cause the a-bits in the receive signal highway bit rsigln to be set to 1 in the transmission mode. the a-bits are present in time slots 3 through 24 in the signaling high- way format. when enlos=1, ais will also be inserted on the receive data high- way when control bit svtais (bit 6) in register x07h is a 1. address bit symbol description superframe n superframe n+1
- 111 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 104 - ch 1 204 - ch 2 304 - ch 3 404 - ch 4 7-6 oof1-oof0 out of frame detection criteria: the oof bits determine the out of frame detection criteria according to the following table: oof1 oof0 out of frame detection criteria 0 0 2 out of 4 frame sync bits in error 0 1 2 out of 5 frame sync bits in error 1 0 2 out of 6 frame sync bits in error 1 1 2 out of 4 frame sync bits in error 5alt alternate yellow alarm: when set to 1, the fs-bit in frame 12 in sf frame for- mat will be enabled for sending a yellow alarm (fs = 1). when this bit is set to 0, the fs bit is transmitted as a 0. this feature is not available for the esf framing format. 4-3 syc1 syc0 frame synchronization bits: these control bits determine which framing bits in the sf and esf frame formats are to be used for frame synchronization (used for the out of frame criteria) according to the table given below. please note that the severely errored frame (sef) criterion is not affected by the set- ting of these bits. syc1 syc0 d 4 sf esf 0 0 not used not used 0 1 fs bits fps bits 1 0 ft bits not used 1 1 fs and ft bits fps and crc-6 bits in d4 sf mode, with frame sync using the fs bits (syc1=0, syc0=1), the frame counter in register xfc will not report ft bit errors. with frame sync using the ft bits (syc1=1, syc0=0), the frame counter at register xfc will not report fs bit errors. 2-1 fmd1 fmd0 framing mode selection bits: these controls bits determine the framing mode according to the table give below: fmd1 fmd0 framing mode 0 0 transparent (no framing) 01 d4 sf 1 0 not used 1 1 esf note: control bits located in per channel internal ram (at addresses x40h- xffh) need to be re-programmed after a change to fmd1 or fmd0. 0rsyc resync enable: a 1 causes the framer to reset the frame alignment circuit, and start the search for a new frame alignment pattern. address bit symbol description
- 112 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 13a - ch 1 23a - ch 2 33a - ch 3 43a - ch 4 7-0 rfd8-rfd1 receive enable fractional ds0 channels 8-1: the receive fractional t1 mode is enabled when control bit ft1m is a 1 and the config1 pin is low (transmission mode). a 1 written to one or more bits enables a gapped clock (rsigl/rft1gc) to be generated for the corresponding ds0 channels (8-1). with the ft1m bit set to 0 in the relevant x02h, the config1 pin either low or high, and this bit for the selected ds0 set to a one, the corresponding ds0 in rdatan is inverted, in transmission or mvip modes. 13b - ch 1 23b - ch 2 33b - ch 3 43b - ch 4 7-0 rfd16- rfd9 receive enable fractional ds0 channels 16-9: the receive fractional t1 mode is enabled when control bit ft1m is a 1 and the config1 pin is low (transmission mode). a 1 written to one or more bits enables a gapped clock (rsigl/rft1gc) to be generated for the corresponding ds0 channels (16-9). with the ft1m bit set to 0 in the relevant x02h, the config1 pin either low or high, and this bit for the selected ds0 set to a one, the corresponding ds0 in rdatan is inverted, in transmission or mvip modes. 13c - ch 1 23c - ch 2 33c - ch 3 43c - ch 4 7-0 rfd24- rfd17 receive enable fractional ds0 channels 24-17: the receive fractional t1 mode is enabled when control bit ft1m is a 1 and the config1 pin is low (transmission mode). a 1 written to one or more bits enables a gapped clock (rsigl/rft1gc) to be generated for the corresponding ds0 channels (24-17). with the ft1m bit set to 0 in the relevant x02h, the config1 pin either low or high, and this bit for the selected ds0 set to a one, the corresponding ds0 in rdatan is inverted, in transmission or mvip modes. 13d - ch 1 23d - ch 2 33d - ch 3 43d - ch 4 7-0 tfd8-tfd1 transmit enable fractional ds0 channels 8-1: the transmit fractional t1 mode is enabled when control bit ft1m is a 1 and the config1 pin is low (transmission mode). a 1 written to one or more bits enables a gapped clock (tsigl/tft1gc) to be generated for the corresponding ds0 channels (8-1). with the ft1m bit set to 0 in the relevant x02h, the config1 pin either low or high, and with this bit for the selected ds0 set to a one, the corresponding ds0 is inverted in tdatan, in transmission or mvip modes. 13e - ch 1 23e - ch 2 33e - ch 3 43e - ch 4 7-0 tfd16-tfd9 transmit enable fractional ds0 channels 16-9: the transmit fractional t1 mode is enabled when control bit ft1m is a 1 and the config1 pin is low (transmission mode). a 1 written to one or more bits enables a gapped clock (tsigl/tft1gc) to be generated for the corresponding ds0 channels (16-9). with the ft1m bit set to 0 in the relevant x02h, the config1 pin either low or high, and with this bit for the selected ds0 set to a one, the corresponding ds0 is inverted in tdatan, in transmission or mvip modes. 13f - ch 1 23f - ch 2 33f - ch 3 43f - ch 4 7-0 tfd24- tfd17 transmit enable fractional ds0 channels 24-17: the transmit fractional t1 mode is enabled when control bit ft1m is a 1 and the config1 pin is low (transmission mode). a 1 written to one or more bits enables a gapped clock (tsigl/tft1gc) to be generated for the corresponding ds0 channels (24-17). with the ft1m bit set to 0 in the relevant x02h, the config1 pin either low or high, and with this bit for the selected ds0 set to a one, the corresponding ds0 is inverted in tdatan, in transmission or mvip modes. address bit symbol description
- 113 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers software reset and loopback control register the control bits in the following read/write register are used to reset each of the channels, and to configure each of the channels within the qt1f- plus for the various loopback modes of operation. address bit symbol description 105 - ch 1 205 - ch 2 305 - ch 3 405 - ch 4 7srst software reset channel n: when set to 1, the channel is initialized and held in the reset state until a 0 is written into this bit position to permit com- mencement of channel operation. 6alup automatic loopback: this control bit is enabled when control bit enpmfm (bit 3 in register 006h) is a 1. when set to 1, a remote line loopback state is entered automatically when a loop-up code match is detected, and cleared automatically when the loop-down code match is detected. the loopback state is entered and cleared if the matches persist for 5 seconds or more. the up and down status bits in register x15h indicate the condition. the loop-up code is determined by control bits lu6 - lu0 (value in register 014h) whose length is defined by the code written to control bits ulen1 and ulen0 (bits 4 and 3 in register 016h). the loop-down code is determined by control bits ld6 - ld0 (value in register 015h) whose length is defined by the code written to control bits dlen1 and dlen0 (bits 1 and 0 in register 016h). 5txup transmit loop-up code enable: when set to 1, the loop-up code as determined by control bits lu6 - lu0 (value in register 014h) whose length is defined by the code written to control bits ulen1 and ulen0 (bits 4 and 3 in register 016h) is transmitted continuously. the loop-up code is released when this bit is set to 0. 4txdn transmit loop-down code enable: when set to 1, the loop-down code as determined by control bits ld6 - ld0 (value in register 015h) whose length is defined by the code written to control bits dlen1 and dlen0 (bits 1 and 0 in register 016h) is transmitted continuously. the loop-down code is released when this bit is set to 0. 3payl payload loopback enable: when set to 1, a payload loopback will be enabled until this bit position is written with a 0. the data and signaling bits from all 24 received ds0s (192 bits per frame) are taken from before the receive slip buffer and are substituted for the data and signaling bits from the transmit slip buffer output and signaling buffer output on a first come first serve basis. only receive bit ordering is maintained. ds0 bit and byte align- ments to the frame bit position are lost. 2tx1s transmit ais (all ones): when set to 1, an ais (all ones) is transmitted instead of data during a local loopback. when set to 0, data is transmitted during a local loopback. 1rlp remote line loopback enable: when set to 1, the remote line loopback feature is enabled until this bit position is written with a 0. receive line data (prior to the b8zs codec) is looped back as transmit line data when this loopback feature is enabled. 0 llp local loopback enable: when set to 1, the local loopback feature is enabled until this bit position is written with a 0. transmit data (after the b8zs codec) is looped back as received data when this loopback feature is enabled. when control bit tx1s (bit 2) is a 0 in register x05h, data is trans- mitted. when tx1s is a 1, ais is transmitted. the ais signal is defined as an all ones signal.
- 114 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers system ais and test registers the control bits in the following read/write registers are used to generate test conditions and to configure the system inter- face for ais in channel (framer) n. address bit symbol description 106 - ch 1 206 - ch 2 306 - ch 3 406 - ch 4 7r reserved: set to 0. 6-5 r reserved: these bit locations do not exist. 4r reserved: set to 0. 3 insprbs insert pseudo-random bit sequence enable: when set to 1, prbs is inserted for the terminal data on the transmit data highway. this feature is only available for transmission mode. to resume normal operation, this bit position must be written with a 0. 2sfz system freeze: when set to 1, the output clocks ltclkn and rclkn are forced to zero. the input clocks lrclkn and tclkn are gated off. to resume normal operation, this bit position must be written with a 0. 1rxfs receive fast sync enable: when set to 1, and the nrz mode is selected, a pulse received on the rnegn lead will force the synchronization of this pulse to be interpreted as bit position 192 of the last frame of a multiframe for either esf or sf format. when set to 0, coding violations indicated on the rnegn lead are counted. 0txfs transmit fast sync enable: when set to 1, and the nrz mode is selected, a synchronization pulse will be transmitted on the tnegn lead every three milli- seconds in bit position 192 of frame 24 for the esf format and every other frame 12 when the sf format is selected.
- 115 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 107 - ch 1 207 - ch 2 307 - ch 3 407 - ch 4 7r reserved: this bit location does not exist. 6 svtais system vtais: when set to 1, the ais, oof and los alarms, if enabled by set- ting to 1 their respective enais (bit 2), enoof (bit 1), and enlos (bit 0) control bits in the signaling and time slot control register x03h, cause the generation of ais on the data highway. the ais is sent until the alarm has recovered, or the enable bit (e.g., enais) is set to 0. the following table lists the operation of con- trol bit enoof and this bit. control bits enais and enlos function in similar fashion. transmission mode enoof svtais action 0 0 no ais generated on signaling or data highway. 0 1 no ais generated on signaling or data highway. 1 0 ais generated only on signaling highway when oof alarm is detected. 1 1 ais generated on signaling and data highways when oof alarm is detected. mvip mode enoof svtais action 0 0 no ais generated on data highway. 0 1 no ais generated on data highway. 1 0 no ais generated on data highway even when oof alarm is detected. 1 1 ais generated on data highway when oof alarm is detected. please note that the microprocessor can cause ais to be generated for the receive data highway independently of the two control bits by writing a 1 to con- trol bit sysall1 (bit 5) in this register. 5 sysall1 send system ais: when set to 1, ais (all ones) is sent on the receive data highway. ais will be transmitted on the receive data highway until this bit is writ- ten with a 0. 4 crc generate one crc-6 error: this feature is enabled when control bits fmd1 and fmd0 (bits 2 and 1) in register x04h are equal to 11 (esf format). when this bit is set to 1, the crc-6 bits in the esf format are transmitted in the inverted state once. to send another crc-6 error, this bit must be first written with a 0, and then a 1. 3frme generate one frame error: when set to 1, the transmitter will send one frame bit (fs, ft or fps) in error once. to transmit another framing error, this bit must be first written with a 0, and then a 1. address bit symbol description
- 116 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers ds1 status and mask registers these registers are read/write, except for registers x10h, which are read-only unlatched. the status bits in the x11h reg- ister represent the latched status indications generated by the channel alarms. the bits latch on either the rising edge, the falling edge, or both edges of the current status or interrupt request event bits as defined by the rise/fall control bits (bits 6 and 5) in the global configuration register 006h. a latched bit will cause a hardware interrupt indication when the global interrupt mask bit gim (bit 7) in register 006h and the corresponding mask bits in the mask registers 00bh and x09h are all written with a 0. the bits in register x10h represent the current (unlatched) alarm status. a latched status bit is reset by writing a 0 into the latched bit position, or by the rising edge of the t1si pulse when the performance monitor- ing/fault monitoring feature is enabled. this feature activates the shadow registers x12h and x13h, and it is enabled by writing a 1 to control bit enpmfm (bit 3) in the global configuration register 006h. 107 - ch 1 207 - ch 2 307 - ch 3 407 - ch 4 (cont.) 2 yel generate yellow alarm indication: when set to 1, the yellow alarm indication is transmitted as a 1 until the microprocessor writes a 0 into this bit position. the yellow alarm is defined as bit 2 in each of 24 ds0 channels equal to 0 for the sf frame format, the fs bit in frame 12 equal to 1 for the japanese sf frame format, and a sequence of eight ones followed by eight zeros (1111111100000000) in the 4 kbit/s data channel for the esf format. 1aise transmit line ais enable: when set to 1, a line ais is transmitted. a line ais is defined as all ones transmitted in the frame. line ais is transmitted until this bit is written with a 0. 0 bpv generate bipolar violation (bpv) error: when the dual unipolar mode is selected by bit 7 in register x00h, a 1 in this bit position causes a single bpv error to be sent. the microprocessor must write a 0 to this bit before another bpv error can be transmitted by setting it to 1. address bit symbol description 109 - ch 1 209 - ch 2 309 - ch 3 409 - ch 4 7mlos loss of signal (los) mask bit: when set to 1, detection of a loss of signal alarm is masked from providing a hardware interrupt. 6mais ais mask bit: when set to 1, detection of an ais condition is masked from pro- viding a hardware interrupt. 5moof out of frame (oof) mask bit: when set to 1, detection of an out of frame alarm is masked from providing a hardware interrupt. 4 myel remote yellow alarm mask bit: when set to 1, detection of a yellow alarm indication is masked from providing a hardware interrupt. 3mcfa/ maisci change in frame alignment (cfa)/ais-ci mask bit: when set to 1, detection of a change in frame alignment (cfa) or the ais-ci signature indication is masked from providing a hardware interrupt. 2msef severely errored frame mask bit: when set to 1, detection of a severely errored frame alarm is masked from providing a hardware interrupt. 1mtxslip transmit slip indication mask bit: when set to 1, detection of a transmit slip is masked from providing a hardware interrupt. 0 mrxslip receive slip indication mask bit: when set to 1, detection of a receive slip is masked from providing a hardware interrupt. address bit symbol description
- 117 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 110 - ch 1 210 - ch 2 310 - ch 3 410 - ch 4 7los loss of signal (los) alarm (unlatched): a 1 indicates a loss of signal has been detected. a loss of signal alarm is detected when the incoming signal for the rail interface only has no transitions for 175 75 consecutive pulse positions. the los alarm is cleared when an average pulse density of at least 12.5% has been received for 175 75 contiguous pulse positions starting with a pulse. in addition, an external los indication from the external line transceiver (using the lintn pin) can be or-gated with this alarm by setting control bit lie (bit 1) in register x00h to 1. 6ais ais indication (unlatched): a 1 indicates that a line alarm indication signal (ais) has been detected. a line ais is detected if 99.9% or more ones are present in the received signal in a period of 48 ms. recovery occurs when the line signal has fewer than 99.9% of ones in a 48 ms period. 5oof out of frame (oof) alarm (unlatched): a 1 indicates that an out of frame alarm has been detected. the alarm is programmed using the oof1 and oof0 control bits (bits 7 and 6) in register x04h. the selection of frame synchroniza- tion bits used for frame alignment is programmed using the syc1 and syc0 control bits (bits 4 and 3) in register 04h. 4 yel yellow alarm (yel) indication (unlatched): a 1 indicates the current state of the yellow alarm. a yellow alarm is detected within 32 ms for the esf format and 335 ms for the sf format, with no line errors present. the alarm is detected within one second in the presence of line errors occurring at the rate of one error in 1000 bits. 3 cfa/aisci change in frame alignment (cfa)/ ais-ci indication (unlatched): a 1 indi- cates that the frame alignment circuit has detected a change in the frame align- ment pattern within the last 125 microseconds only after frame alignment has been detected. if ais is true, this bit also indicates that the ais-ci signature has been detected twice or more. the ais-ci signature is an all ones pattern logi- cally ? anded ? with the code 1111 1111 0011 1110 (left to right), one bit of the code every 386 bits. this signature pattern typically repeats every 4 milliseconds for approximately 150 milliseconds, followed by 1.11 seconds of all ones, with the entire 1.26 second pattern repeating as long as the alarm persists. 2sef severely errored frame (sef) indication: a 1 indicates a severely errored frame has been detected in the previous 125 microseconds. for the sf format, an sef indication occurs if two or more frame bit errors (ft bit only) are detected within a 0.75 ms period. for the esf format, sef is declared when two or more frame bit errors occur over a 3.0 ms period. recovering occurs when fewer then two errors are detected for the periods indicated for the two frame formats (sf and esf). 1txslip transmit slip indication (unlatched): this bit reflects the current status of the transmit slip buffer with respect to a slip being executed in the previous 125 microseconds. 0 rxslip receive slip indication (unlatched): this bit reflects the current status of the receive slip buffer with respect to a slip being executed in the previous 125 microseconds. address bit symbol description
- 118 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 111 - ch 1 211 - ch 2 311 - ch 3 411 - ch 4 7 llos latched loss of signal (los): this bit is set to 1 on an active edge of los which is selected by the rise (bit 6) and fall (bit 5) bits in the global configu- ration register 006h. if not masked by the corresponding mask bit in register x09h or the gim bit in register 006h, an interrupt is generated. this bit is cleared by writing a 0 into this bit position. 6lais latched ais: this bit is set to 1 on an active edge of ais which is selected by the rise (bit 6) and fall (bit 5) bits in the global configuration register 006h. if not masked by the corresponding mask bit in register x09h or the gim bit in register 006h, an interrupt is generated. this bit is cleared by writing a 0 into this bit position. 5 loof latched out of frame (oof): this bit is set to 1 on an active edge of oof which is selected by the rise (bit 6) and fall (bit 5) bits in the global configu- ration register 006h. if not masked by the corresponding mask bit in register x09h or the gim bit in register 006h, an interrupt is generated. this bit is cleared by writing a 0 into this bit position. 4lyel latched yellow alarm (yel) indication: this bit is set to 1 on an active edge of yel which is selected by the rise (bit 6) and fall (bit 5) bits in the global con- figuration register 006h. if not masked by the corresponding mask bit in register x09h or the gim bit in register 006h, an interrupt is generated. this bit is cleared by writing a 0 into this bit position. 3lcfa/ laisci latched change in frame alignment (cfa)/ais-ci indication: this bit is set to 1 on an active edge of cfa/aisci which is selected by the rise (bit 6) and fall (bit 5) bits in the global configuration register 006h. if not masked by the corresponding mask bit in register x09h or the gim bit in register 006h, an inter- rupt is generated. this bit is cleared by writing a 0 into this bit position. 2 lsef latched severely errored frame (sef) indication: this bit is set to 1 on an active edge of sef which is selected by the rise (bit 6) and fall (bit 5) bits in the global configuration register 006h. if not masked by the corresponding mask bit in register x09h or the gim bit in register 006h, an interrupt is gener- ated. this bit is cleared by writing a 0 into this bit position. 1 ltxslip latched transmit slip indication: this bit is set to 1 on an active edge of txslip which is selected by the rise (bit 6) and fall (bit 5) bits in the global configuration register, location 006h. if not masked by the corresponding mask bit in register x09h or the gim bit in register 006h, an interrupt is generated. this bit is cleared by writing a 0 into this bit position. 0lrxslip latched receive slip indication: this bit is set to 1 on an active edge of rxslip which is selected by the rise (bit 6) and fall (bit 5) bits in the global configuration register 006h. if not masked by the corresponding mask bit in register x09h or the gim bit in register 006h, an interrupt is generated. this bit is cleared by writing a 0 into this bit position. address bit symbol description
- 119 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 112 - ch 1 212 - ch 2 312 - ch 3 412 - ch 4 7plos loss of signal (los) one second error: this bit is set to 1 if the los alarm occurred at any time in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register x006h must be set to 1. 6pais ais one second error: this bit is set to 1 if the ais indication occurred at any time in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. 5poof out of frame (oof) one second error: this bit is set to 1 if the oof alarm occurred at any time in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. 4 pyel yellow alarm (yel) indication one second error: this bit is set to 1 if the yel indication occurred at any time in the last one second interval. the t1si sig- nal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. 3pcfa/ pa i s c i change in frame alignment (cfa)/ais-ci one second error: this bit is set to 1 if the cfa/aisci indication occurred at any time in the last one second inter- val. the t1si signal must be present and control bit enpmfm (bit 3) in the glo- bal configuration register 006h must be set to 1. 2psef severely errored frame (sef) indication one second error: this bit is set to 1 if the sef alarm occurred at any time in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configura- tion register 006h must be set to 1. 1ptxslip transmit slip indication one second error: this bit is set to 1 if the txslip indication occurred at any time in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register x006h must be set to 1. 0prxslip receive slip indication one second error: this bit is set to 1 if the rxslip indication occurred at any time in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. address bit symbol description
- 120 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 113 - ch 1 213 - ch 2 313 - ch 3 413 - ch 4 7flos loss of signal (los) persistent error: this bit is set to 1 if the los alarm is active but did not become active in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. 6fais ais persistent error: this bit is set to 1 if the ais indication is active but did not become active in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. 5foof out of frame (oof) persistent error: this bit is set to 1 if the oof alarm is active but did not become active in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register x006h must be set to 1. 4fyel yellow alarm (yel) indication persistent error: this bit is set to 1 if the yel indication is active but did not become active in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global con- figuration register 006h must be set to 1. 3fcfa/ faisci change in frame alignment (cfa) /ais-ci persistent error: this bit is set to 1 if the cfa/aisci indication is active but did not become active in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register x006h must be set to 1. 2fsef severely errored frame (sef) persistent error: this bit is set to 1 if the sef alarm is active but did not become active in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global con- figuration register 006h must be set to 1. 1ftxslip transmit slip indication persistent error: this bit is set to 1 if the txslip indi- cation is active but did not become active in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global con- figuration register 006h must be set to 1. 0 frxslip receive slip indication persistent error: this bit is set to 1 if the rxslip indication is active but did not become active in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. address bit symbol description
- 121 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers counters and counter shadow registers the qt1f- plus provides counter and counter shadow read/write registers for crc-6 bit errors, coding violations (with or without excess zeros), and framing errors. the counter shadow registers provide the microprocessor with an error count for the previous one second interval. a counter and the corresponding counter shadow register (and their overflow bits) are cleared when the microprocessor writes 0 to their bits. when the shadow register feature is enabled by writing a 1 to control bit enpmfm (bit 3) in the global configuration register 006h, the rising edges of a one second interval pulse also clear the counters (and the overflow bits, if set). the shadow registers for the various counters are also updated at one second intervals by the rising edge of the pulse applied to the t1si pin (pin 40). address bit symbol description 1f0 - ch 1 2f0 - ch 2 3f0 - ch 3 4f0 - ch 4 7-0 lcrc7-lcrc0 latched crc-6 error counter shadow register: enabled when control bit enpmfm (bit 3) in register 006h is a 1, and a one second signal is applied to the t1si pin. this register contains the lower 8 bits of the 9-bit shadow register assigned for holding the crc-6 error count that occurred in the previous one second interval. this location is updated from crc7- crc0 with a new count at one second intervals on the rising edges of the t1si signal. bit 0 is the lsb of the 9-bit count. 1f1 - ch 1 2f1 - ch 2 3f1 - ch 3 4f1 - ch 4 7 lcrco latched crc-6 error counter overflow bit: enabled when control bit enpmfm (bit 3) in register 006h is a 1, and a one second signal is applied to the t1si pin. this bit contains the overflow indication associated with the 9-bit shadow register lcrc8-lcrc0 assigned for holding the crc-6 error count that occurred in the previous one second interval. this location is updated from crco at one second intervals on the rising edges of the t1si signal. 6-1 r reserved : set to 0. 0 lcrc8 latched crc-6 error counter shadow register: enabled when control bit enpmfm (bit 3) in register 006h is a 1, and a one second signal is applied to the t1si pin. this register contains the highest bit of the 9-bit shadow register assigned for holding the crc-6 error count that occurred in the previous one second interval. this location is updated from crc8 with a new count at one second intervals on the rising edges of the t1si signal. bit 0 is the msb of the 9-bit count. 1f2 - ch 1 2f2 - ch 2 3f2 - ch 3 4f2 - ch 4 7-0 crc7-crc0 crc-6 error counter: this register contains the lower 8 bits of the 9-bit crc-6 error counter. when control bit enpmfm (bit 3) in register 006h is a 1, this location is cleared at one second intervals on the rising edges of the t1si signal. bit 0 is the lsb of the 9-bit count. 1f3 - ch 1 2f3 - ch 2 3f3 - ch 3 4f3 - ch 4 7 crco crc-6 error counter overflow bit: this bit contains the overflow indica- tion associated with the 9-bit crc-6 counter crc8-crc0. this bit sets when the 9-bit counter overflows. it will remain set until the microprocessor writes a 0 into this location. when control bit enpmfm (bit 3) in register 006h is a 1, this location is also cleared at one second intervals on the rising edges of the t1si signal. 6-1 r reserved : set to 0. 0 crc8 crc-6 error counter: this register contains the highest bit of the 9-bit crc-6 error counter. when control bit enpmfm (bit 3) in register 006h is a 1, this location is cleared at one second intervals on the rising edges of the t1si signal. bit 0 is the msb of the 9-bit count.
- 122 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 1f4 - ch 1 2f4 - ch 2 3f4 - ch 3 4f4 - ch 4 7-0 lcv7-lcv0 latched coding violation counter shadow register: enabled when control bit enpmfm (bit 3) in register 006h is a 1, and a one second signal is applied to the t1si pin. this register contains the lower 8 bits of the 16-bit shadow register assigned for holding the b8zs coding violation / excess zeros count that occurred in the previous one second interval. this location is updated from cv7-cv0 with a new count at one second intervals on the rising edges of the t1si signal. bit 0 is the lsb of the 16-bit count. 1f5 - ch 1 2f5 - ch 2 3f5 - ch 3 4f5 - ch 4 7-0 lcv15-lcv8 latched coding violation counter shadow register: enabled when control bit enpmfm (bit 3) in register 006h is a 1, and a one second signal is applied to the t1si pin. this register contains the upper 8 bits of the 16-bit shadow register assigned for holding the b8zs coding violation / excess zeros count that occurred in the previous one second interval. this location is updated from cv15-cv8 with a new count at one second intervals on the rising edges of the t1si signal. bit 7 is the msb of the 16-bit count. 1f6 - ch 1 2f6 - ch 2 3f6 - ch 3 4f6 - ch 4 7lcvo latched coding violation counter overflow bit: enabled when control bit enpmfm (bit 3) in register 006h is a 1, and a one second signal is applied to the t1si pin. this bit contains the overflow indication associated with the 16-bit shadow register lcv15-lcv0 assigned for holding the b8zs coding violation / excess zeros count that occurred in the previous one sec- ond interval. this location is updated from cvo at one second intervals on the rising edges of the t1si signal. 6-0 r reserved : set to 0. 1f7 - ch 1 2f7 - ch 2 3f7 - ch 3 4f7 - ch 4 7-0 cv7-cv0 coding violation counter: this register contains the lower 8 bits of the 16- bit b8zs coding violation / excess zeros counter. when control bit enpmfm (bit 3) in register 006h is a 1, this location is cleared at one second intervals on the rising edges of the t1si signal. bit 0 is the lsb of the 16-bit count. 1f8 - ch 1 2f8 - ch 2 3f8 - ch 3 4f8 - ch 4 7-0 cv15-cv8 coding violation counter: this register contains the upper 8 bits of the 16- bit b8zs coding violation / excess zeros counter. when control bit enpmfm (bit 3) in register 006h is a 1, this location is cleared at one second intervals on the rising edges of the t1si signal. bit 7 is the msb of the 16-bit count. 1f9 - ch 1 2f9 - ch 2 3f9 - ch 3 4f9 - ch 4 7cvo coding violation counter overflow bit: this bit contains the overflow indication associated with the 16-bit b8zs coding violation / excess zeros counter cv15-cv0. this bit sets when the 16-bit counter overflows. it will remain set until the microprocessor writes a 0 into this location. when con- trol bit enpmfm (bit 3) in register 006h is a 1, this location is also cleared at one second intervals on the rising edges of the t1si signal. 6-0 r reserved : these bit locations do not exist. 1fa - ch 1 2fa - ch 2 3fa - ch 3 4fa - ch 4 7-0 lfbe7-lfbe0 latched framing bit error counter shadow register: enabled when control bit enpmfm (bit 3) in register 006h is a 1, and a one second signal is applied to the t1si pin. this register contains the 8-bit count of the fram- ing bit errors that occurred in the previous one second interval. this location is updated from fbe7-fbe0 with a new count at one second intervals on the rising edges of the t1si signal. address bit symbol description
- 123 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 1fb - ch 1 2fb - ch 2 3fb - ch 3 4fb - ch 4 7 lfbeo latched framing bit error counter overflow bit: enabled when control bit enpmfm (bit 3) in register 006h is a 1, and a one second signal is applied to the t1si pin. this bit contains the overflow indication associated with the 8-bit shadow register lfbe7-lfbe0 assigned for holding the fram- ing bit error count that occurred in the previous one second interval. this location is updated from fbeo at one second intervals on the rising edges of the t1si signal. 6-0 r reserved : set to 0. 1fc - ch 1 2fc - ch 2 3fc - ch 3 4fc - ch 4 7-0 fbe7-fbe0 framing bit error counter: this register contains the 8-bit framing bit error count. when control bit enpmfm (bit 3) in register 006h is a 1, this location is cleared at one second intervals on the rising edges of the t1si signal. 1fd - ch 1 2fd - ch 2 3fd - ch 3 4fd - ch 4 7fbeo framing bit error counter overflow bit: this bit contains the overflow indication associated with the 8-bit framing bit error counter fbe7-fbe0. this bit sets when the 8-bit counter overflows. it will remain set until the microprocessor writes a 0 into this location. when control bit enpmfm (bit 3) in register 006h is a 1, this location is also cleared at one second intervals on the rising edges of the t1si signal. 6-0 r reserved : set to 0. address bit symbol description
- 124 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers operational status registers the status bits in the following read-only unlatched registers indicate various status information associated with the transmit and receive two-frame slip buffers. the slip buffers are always enabled in the mvip mode (config1 pin is high - pin 43). the slip buffers are optional in the transmission mode (config1 pin is low - pin 43). the transmit slip buffer is enabled when a 1 is written into control bit tse (bit 4) in register x02h. the receive slip buffer is enabled when a 1 is written into control bit rse (bit 3) in register x02h. address bit symbol description 114 - ch 1 214 - ch 2 314 - ch 3 414 - ch 4 7-6 txs1-tsx0 transmit slip buffer status: the following table indicates the direction of a transmit slip. a transmit slip indication (unlatched) is provided by status bit txslip (bit 1) set to 1 in register x10h. a latched indication is given by ltxslip (bit 1) set to 1 in register x11h. txs1 txso b uffer status 0 0 no slips have occurred. 0 1 slip overflow. one frame dropped. 1 0 slip underflow. one frame repeated. 1 1 slip buffer error. two slips in a row. 5-4 rxs1-rxs0 receive slip buffer status: the following table indicates the direction of a receive slip. a receive slip indication (unlatched) is provided by status bit rxslip (bit 0) set to 1 in register x10h. a latched indication is given by lrxslip (bit 0) set to 1 in register x11h. rxs1 rxso b uffer status 0 0 no slips have occurred. 0 1 slip overflow. one frame dropped. 1 0 slip underflow. one frame repeated. 1 1 slip buffer error. two slips in a row. 3vtais vt ais received: this status bit is enabled in the transmission mode only. a 1 indicates that the (ais) a-bits on the transmit signaling highway (tsigln) are set to 1. the response time and recovery times are immediate. 2 vtrdi vt rdi received: this status bit is enabled in the transmission mode only. a 1 indicates that the remote defect indication (y) bit on the transmit sig- naling highway (tsigln) is set to 1. the response time and recovery times are immediate. 1-0 r reserved : disregard these bits.
- 125 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers slip buffer pointer status registers the following read-only unlatched register locations provide receive read and write pointer information, and transmit read and write pointer information, from the receive and transmit slip buffers respectively. please note that the sixteen register pairs x20h/x21h, x22h/x23h, x24h/x25h and x26h/x27h (where x=1, 2, 3 or 4) are constructed for 16-bit word read operations. each pair must always be read in two consecutive read operations, with the even-numbered register being read first, e.g., 120h followed by 121h. if either register is read, the other will always be accessed for the next read operation, regardless of the address then selected. if the odd-numbered register is accessed first, data may be corrupted for both read operations. there is no such restriction on write operations. 115 - ch 1 215 - ch 2 315 - ch 3 415 - ch 4 7rxsf receive signaling freeze indication: when set to 1, this status bit indicates that the receive signaling bits in the signaling buffer are frozen as a result of a loss of signal or out of frame alarm, or that control bit rxf (bit 5) in register x03h is a 1. 6 txsf transmit signaling freeze indication: when set to 1, this status bit indi- cates that the transmit signaling bits in the signaling buffer are frozen as a result of receiving an ais indication on the signaling highway in the trans- mission mode, or that control bit txf (bit 4) in register x03h is a 1. 5-3 r reserved : disregard these bits. 2up receive loop-up code indication: this feature is enabled by control bit alup (bit 6) in register x05h being set to a 1 as well as control bit enpmfm (bit 3) in register 006h being set to a 1. when set to 1 this status bit indicates that a valid loop-up code, as defined by control bits lu6 - lu0 and ulen1, ulen0 in registers 014h and 016h, has been detected. the receipt of a valid loop-up code de-asserts the down bit in this register. after receiving the loop-up code for 5 seconds, remote line loopback is entered. 1down receive loop-down code indication: when set to 1, this status bit indi- cates that a valid loop-down code, as defined by control bits ld6 - ld0 and dlen1, dlen0 in registers 015h and 016h, has been detected. after receiving the loop-down code for 5 seconds, the remote line loopback con- dition is released. at initialization, this bit is set to 1, and after a loop-up code is received, the up indication in this register is set and this bit is cleared. 0lint general purpose input status indication: the status of this bit reflects the state of the external input pin lintn. the input polarity (i.e., active state) of this pin is determined by control bit lpol (bit 0) in register x00h. the bit lint is 1 when the pin is active. address bit symbol description 120 - ch 1 220 - ch 2 320 - ch 3 420 - ch 4 7-0 twp7-twp0 transmit slip buffer write pointer: bit 0 is the lsb. the value (between 0 and 192) is the current value of the transmit slip buffer write pointer. address bit symbol description
- 126 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 121 - ch 1 221 - ch 2 321 - ch 3 421 - ch 4 7-0 trp7-trp0 transmit slip buffer read pointer: bit 0 is the lsb. the value (between 0 and 192) is the current value of the transmit slip buffer read pointer. 122 - ch 1 222 - ch 2 322 - ch 3 422 - ch 4 7 twsbs transmit slip buffer write side: a 1 indicates that the upper side of the transmit slip buffer is currently being written, a 0 indicates that the lower side of the transmit slip buffer is being written. 6-5 r reserved : disregard these bits. 4-0 twpf4-twpf0 transmit slip buffer write pointer frame: the bits in these locations indicate for which frame the transmit slip buffer write pointer is being written. for the sf format the value will range between 0 and 11 and for the esf format the value will range between 0 and 23. bit 0 is the lsb. 123 - ch 1 223 - ch 2 323 - ch 3 423 - ch 4 7 trsbs transmit slip buffer read side: a 1 indicates that the upper side of the transmit slip buffer is currently being read, a 0 indicates that the lower side of the transmit slip buffer is being read. 6-5 r reserved : disregard these bits. 4-0 trpf4-trpf0 transmit slip buffer read pointer frame: the bits in these locations indicate for which frame the transmit slip buffer read pointer is being read. for the sf format the value will range between 0 and 11 and for the esf format the value will range between 0 and 23. bit 0 is the lsb. 124 - ch 1 224 - ch 2 324 - ch 3 424 - ch 4 7-0 rwp7-rwp0 receive slip buffer write pointer: bit 0 is the lsb. the value (between 0 and 192) is the current value of the receive slip buffer write pointer. 125 - ch 1 225 - ch 2 325 - ch 3 425 - ch 4 7-0 rrp7-rrp0 receive slip buffer read pointer: bit 0 is the lsb. the value (between 0 and 192) is the current value of the receive slip buffer read pointer. 126 - ch 1 226 - ch 2 326 - ch 3 426 - ch 4 7rwsbs receive slip buffer write side: a 1 indicates that the upper side of the receive slip buffer is currently being written. a 0 indicates that the lower side of the receive slip buffer is being written. 6-5 r reserved : disregard these bits. 4-0 rwpf4-rwpf0 receive slip buffer write pointer frame: the bits in these locations indi- cate for which frame the receive slip buffer write pointer is being written. for the sf format the value will range between 0 and 11 and for the esf format the value will range between 0 and 23. bit 0 is the lsb. 127 - ch 1 227 - ch 2 327 - ch 3 427 - ch 4 7rrsbs receive slip buffer read side: a 1 indicates that the upper side of the receive slip buffer is currently being read, a 0 indicates that the lower side of the receive slip buffer is being read. 6-5 r reserved : disregard these bits. 4-0 rrpf4-rrpf0 receive slip buffer read pointer frame: the bits in these locations indi- cate for which frame the receive slip buffer read pointer is being read. for the sf format the value will range between 0 and 11 and for the esf format the value will range between 0 and 23. bit 0 is the lsb. address bit symbol description
- 127 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers receive time slot control registers the control bits in the following read/write registers are used to enable or disable (freeze) the receive slip buffer locations for the system highway, and to allow the microprocessor to write in service codes and idle codes. address bit symbol description 1e0 - ch 1 2e0 - ch 2 3e0 - ch 3 4e0 - ch 4 7-0 rde8-rde1 receive ds0 channel enable for ds0 channels 8-1: when a bit in this register is set to 1, the corresponding received ds0 channel is written into the slip buffer. the ds0 channel is then read from the slip buffer for the receive data highway. when a bit in this register is written with a 0, the corre- sponding ds0 channel will not be written into the slip buffer. instead, the microprocessor writes the value of the ds0 channel into the slip buffer and this value will be read from the slip buffer for the receive data highway. bit 7 is assigned to receive ds0 channel 8. the slip buffers are located in regis- ters x47h-x40h (frame 1) and x5fh-x58h (frame 2). 1e1 - ch 1 2e1 - ch 2 3e1 - ch 3 4e1 - ch 4 7-0 rde16-rde9 receive ds0 channel enable for ds0 channels 16-9: when a bit in this register is set to 1, the corresponding received ds0 channel is written into the slip buffer. the ds0 channel is then read from the slip buffer for the receive data highway. when a bit in this register is written with a 0, the corre- sponding ds0 channel will not be written into the slip buffer. instead, the microprocessor writes the value of the ds0 channel into the slip buffer and this value will be read from the slip buffer for the receive data highway. bit 7 is assigned to receive ds0 channel 16. the slip buffers are located in regis- ters x4fh-x48h (frame 1) and x67h-x60h (frame 2). 1e2 - ch 1 2e2 - ch 2 3e2 - ch 3 4e2 - ch 4 7-0 rde24-rde17 receive ds0 channel enable for ds0 channels 24-17: when a bit in this register is set to 1, the corresponding received ds0 channel is written into the slip buffer. the ds0 channel is then read from the slip buffer for the receive data highway. when a bit in this register is written with a 0, the corre- sponding ds0 channel will not be written into the slip buffer. instead, the microprocessor writes the value of the ds0 channel into the slip buffer and this value will be read from the slip buffer for the receive data highway. bit 7 is assigned to receive ds0 channel 24. the slip buffers are located in regis- ters x57h-x50h (frame 1) and x6fh-x68h (frame 2).
- 128 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers receive time slot registers the bits in these read/write registers are the receive time slots from the ds1 frame format (sf or esf) that are present in the two-frame slip buffer, when enabled. please note that, on loss of frame alignment, the states present in the slip buffer will be frozen to the states existing prior to the loss of frame alignment. address bit symbol description 140-157 - ch 1 240-257 - ch 2 340-357 - ch 3 440-457 - ch 4 7-0 rds0(1)- rds0(24) receive ds0c: register locations x40h-x57h represent frame 1 in the two frame slip buffer for the data highway. the register loca- tions for a ds0 channel are enabled when the corresponding receive ds0 channel enable bits (rde1-rde24) in registers xe0h, xe1h and xe2h are written with 1. when one or more control bits in registers xe0h-xe2h are written with a 0, the corresponding receive ds0 channel is disabled from being written into the buffer location, and the corresponding values in the two register locations are frozen. the microprocessor can now write an idle or service code to the corresponding buffer location. please note that both frame locations in the slip buffer must be written for a ds0 channel (see registers x90h - xa7h below). 158-16f - ch 1 258-26f - ch 2 358-36f - ch 3 458-46f - ch 4 7-0 rds0(1)- rds0(24) receive ds0c: register locations x58h-x6fh represent frame 2 in the two frame slip buffer for the data highway. the register loca- tions for a ds0 channel are enabled when the corresponding receive ds0 channel enable bits (rde1-rde24) in registers xe0h, xe1h and xe2h are written with 1. when one or more control bits in registers xe0h-xe2h are written with a 0, the corresponding receive ds0 channel is disabled from being written into the buffer location, and the corresponding values in the two register locations are frozen. the microprocessor can now write an idle or service code to the corresponding buffer location. please note that both frame locations in the slip buffer must be written for a ds0 channel (see registers xa8h - xbfh below).
- 129 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers transmit time slot control registers the control bits in the following read/write registers are used to enable or disable (freeze) the transmit slip buffer location s for receiving input from the system highway, and to allow the microprocessor to write in service codes and idle codes. address bit symbol description 1e4 - ch 1 2e4 - ch 2 3e4 - ch 3 4e4 - ch 4 7-0 tde8-tde1 transmit ds0 enable for ds0 channels 8-1: when a bit in this register is set to 1, the corresponding transmit ds0 channel from the transmit data highway is written into the slip buffer. the ds0 channel is then read from the slip buffer for the transmit line. when a bit in this register is written with a 0, the corresponding ds0 channel from the data highway will not be written into the slip buffer. instead, the microprocessor writes the value of the ds0 channel into the slip buffer and this value will be read from the slip buffer for the transmit line. bit 7 is assigned to transmit ds0 channel 8. the slip buffers are located in registers x97h-x90h (frame 1) and xafh-xa8h (frame 2). 1e5 - ch 1 2e5 - ch 2 3e5 - ch 3 4e5 - ch 4 7-0 tde16-tde9 transmit ds0 enable for ds0 channels 16-9: when a bit in this register is set to 1, the corresponding transmit ds0 channel from the transmit data highway is written into the slip buffer. the ds0 channel is then read from the slip buffer for the transmit line. when a bit in this register is written with a 0, the corresponding ds0 channel from the data highway will not be written into the slip buffer. instead, the microprocessor writes the value of the ds0 channel into the slip buffer and this value will be read from the slip buffer for the transmit line. bit 7 is assigned to transmit ds0 channel 16. the slip buffers are located in registers x9fh-x98h (frame 1) and xb7h-xb0h (frame 2). 1e6 - ch 1 2e6 - ch 2 3e6 - ch 3 4e6 - ch 4 7-0 tde24-tde17 transmit ds0 enable for ds0 channels 24-17: when a bit in this register is set to 1, the corresponding transmit ds0 channel from the transmit data highway is written into the slip buffer. the ds0 channel is then read from the slip buffer for the transmit line. when a bit in this register is written with a 0, the corresponding ds0 channel from the data highway will not be written into the slip buffer. instead, the microprocessor writes the value of the ds0 channel into the slip buffer and this value will be read from the slip buffer for the transmit line. bit 7 is assigned to transmit ds0 channel 24. the slip buffers are located in registers xa7h-xa0h (frame 1) and xbfh-xb8h (frame 2).
- 130 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers transmit time slot registers the bits in these read/write registers are the transmit time slots from the ds1 frame format that are present in the two- frame slip buffer, when enabled. address bit symbol description 190-1a7 - ch 1 290-2a7 - ch 2 390-3a7 - ch 3 490-4a7 - ch 4 7-0 tds0(1)- tds0(24) transmit ds0c: register locations x90h-xa7h represent frame 1 in the two-frame slip buffer from the data highway. the register locations for a ds0 channel are enabled when the corresponding transmit ds0 channel enable bits (tde1 - tde24) in registers xe4h, xe5h and xe6h are writ- ten with 1. when one or more control bits in registers xe4h-xe6h are written with a 0, the corresponding transmit ds0 channel is disabled from being written into the buffer location, and the corresponding values in the register locations are frozen. the microprocessor can now write an idle or service code to the corresponding slip buffer location. please note that both frame locations in the slip buffer must be written for a ds0 channel. 1a8-1bf - ch 1 2a8-2bf - ch 2 3a8-3bf - ch 3 4a8-4bf - ch 4 7-0 tds0(1)- tds0(24) transmit ds0c: register locations xa8h-xbfh represent frame 2 in the two-frame slip buffer from the data highway. the register locations for a ds0 channel are enabled when the corresponding transmit ds0 channel enable bits (tde1 - tde24) in registers xe4h, xe5h and xe6h are written with 1. when one or more control bits in registers xe4h-xe6h are written with a 0, the corresponding transmit ds0 channel is disabled from being written into the buffer location, and the corresponding values in the register locations are frozen. the micro- processor can now write an idle or service code to the corresponding slip buffer location. please note that both frame locations in the slip buffer must be written for a ds0 channel.
- 131 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers signaling control registers the bits in the following read/write registers control both the receive and transmit signaling buffer locations for ds0 chan- nels 1 through 24. address bit symbol description 1e8 - ch 1 2e8 - ch 2 3e8 - ch 3 4e8 - ch 4 7-0 se8-se1 signaling enable for ds0 channels 8-1: when a bit in this register is set to 1, the transmit and receive signaling bits for the corresponding telephone channel are enabled. the signaling bits are written into the transmit and receive signaling buffers from the transmit signaling highway and the receive line, and are inserted into the transmit line and receive signaling highway. when sec is set to 0, or changes from 1 to 0, the signaling states for the corresponding ds0c in the receive signaling buffers are set to 0. the abili- ties to internally write the signaling bits from the receive line into the receive signaling buffers, or to update the receive signaling buffer from the micropro- cessor, or to insert robbed bits into the transmit line ds0 channel, are dis- abled. bit 7 is the enable bit for ds0 channel 8. 1e9 - ch 1 2e9 - ch 2 3e9 - ch 3 4e9 - ch 4 7-0 se16-se9 signaling enable for ds0 channels 16-9: when a bit in this register is set to 1, the transmit and receive signaling bits for the corresponding telephone channel are enabled. the signaling bits are written into the transmit and receive signaling buffers from the transmit signaling highway and the receive line, and are inserted into the transmit line and receive signaling highway. when sec is set to 0, or changes from 1 to 0, the signaling states for the corresponding ds0c in the receive signaling buffers are set to 0. the abili- ties to internally write the signaling bits from the receive line into the receive signaling buffers, or to update the receive signaling buffer from the micropro- cessor, or to insert robbed bits into the transmit line ds0 channel, are dis- abled. bit 7 is the enable bit for ds0 channel 16. 1ea - ch 1 2ea - ch 2 3ea - ch 3 4ea - ch 4 7-0 se24-se17 signaling enable for ds0 channels 24-17: when a bit in this register is set to 1, the transmit and receive signaling bits for the corresponding tele- phone channel are enabled. the signaling bits are written into the transmit and receive signaling buffers from the transmit signaling highway and the receive line, and are inserted into the transmit line and receive signaling highway. when sec is set to 0, or changes from 1 to 0, the signaling states for the corresponding ds0c in the receive signaling buffers are set to 0. the abilities to internally write the signaling bits from the receive line into the receive signaling buffers, or to update the receive signaling buffer from the microprocessor, or to insert robbed bits into the transmit line ds0 channel, are disabled. bit 7 is the enable bit for ds0 channel 24.
- 132 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers receive and transmit signaling registers the following read/write register locations contain the signaling states associated with each of the ds0 channels carried in the sf or esf frame. when the signaling states for a channel are frozen, the microprocessor can write a new signaling state using the following registers. address bit symbol description 180 - ch 1 280 - ch 2 380 - ch 3 480 - ch 4 7-0 received signaling bits a8-a1 receive a8-a1 signaling bits: the signaling bits in this register are the states of the received a1 to a8 bits in the receive signaling buffer. bit 7 is the a8 signal- ing bit value. please note that a receive signaling state is written into the signal- ing buffer when the corresponding ds0 channel enable bit sec is written with a 1 (where c is the ds0 channel number, from 1 to 24). when the corresponding ds0 channel enable bit sec is written with a 0, zeros are written into the buffer for the ds0 ? s a-signaling bits. 181 - ch 1 281 - ch 2 381 - ch 3 481 - ch 4 7-0 received signaling bits a16-a9 receive a16-a9 signaling bits: the signaling bits in this register are the states of the received a9-a16 bits in the receive signaling buffer. bit 7 is the a16 signal- ing bit value. please note that a receive signaling state is written into the signal- ing buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit sec is written with a 0, zeros are written into the buffer for the ds0 ? s a-signaling bits. 182 - ch 1 282 - ch 2 382 - ch 3 482 - ch 4 7-0 received signaling bits a24-a17 receive a24-a17 signaling bits: the signaling bits in this register are the states of the received a17-a24 bits in the receive signaling buffer. bit 7 is the a24 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit sec is written with a 0, zeros are written into the buffer for the ds0 ? s a-signaling bits. 184 - ch 1 284 - ch 2 384 - ch 3 484 - ch 4 7-0 received signaling bits b8-b1 receive b8-b1 signaling bits: the signaling bits in this register are the states of the received b1 to b8 bits in the receive signaling buffer. bit 7 is the b8 signal- ing bit value. please note that a receive signaling state is written into the signal- ing buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit sec is written with a 0, zeros are written into the buffer for the ds0 ? s b-signaling bits. 185 - ch 1 285 - ch 2 385 - ch 3 485 - ch 4 7-0 received signaling bits b16-b9 receive b16-b9 signaling bits: the signaling bits in this register are the states of the received b9 to b16 bits in the receive signaling buffer. bit 7 is the b16 sig- naling bit value. please note that a receive signaling state is written into the sig- naling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit sec is written with a 0, zeros are written into the buffer for the ds0 ? s b-signaling bits. 186 - ch 1 286 - ch 2 386 - ch 3 486 - ch 4 7-0 received signaling bits b24-b17 receive b24-b17 signaling bits: the signaling bits in this register are the states of the received b17 to b24 bits in the receive signaling buffer. bit 7 is the b24 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is writ- ten with a 1. when the corresponding ds0 channel enable bit sec is written with a 0, zeros are written into the buffer for the ds0 ? s b-signaling bits. 188 - ch 1 288 - ch 2 388 - ch 3 488 - ch 4 7-0 received signaling bits c8-c1 receive c8-c1 signaling bits: the signaling bits in this register are the states of the received c1 to c8 bits in the receive signaling buffer. bit 7 is the c8 signal- ing bit value. please note that a receive signaling state is written into the signal- ing buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit sec is written with a 0, zeros are written into the buffer for the ds0 ? s c-signaling bits.
- 133 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 189 - ch 1 289 - ch 2 389 - ch 3 489 - ch 4 7-0 received signaling bits c16-c9 receive c16-c9 signaling bits: the signaling bits in this register are the states of the received c9 to c16 bits in the receive signaling buffer. bit 7 is the c16 sig- naling bit value. please note that a receive signaling state is written into the sig- naling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit sec is written with a 0, zeros are written into the buffer for the ds0 ? s c-signaling bits. 18a - ch 1 28a - ch 2 38a - ch 3 48a - ch 4 7-0 received signaling bits c24-c17 receive c24-c17 signaling bits: the signaling bits in this register are the states of the received c17 to c24 bits in the receive signaling buffer. bit 7 is the c24 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is writ- ten with a 1. when the corresponding ds0 channel enable bit sec is written with a 0, zeros are written into the buffer for the ds0 ? s c-signaling bits. 18c - ch 1 28c - ch 2 38c - ch 3 48c - ch 4 7-0 received signaling bits d8-d1 receive d8-d1 signaling bits: the signaling bits in this register are the states of the received d1 to d8 bits in the receive signaling buffer. bit 7 is the d8 signal- ing bit value. please note that a receive signaling state is written into the signal- ing buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit sec is written with a 0, zeros are written into the buffer for the ds0 ? s d-signaling bits. 18d - ch 1 28d - ch 2 38d - ch 3 48d - ch 4 7-0 received signaling bits d16-d9 receive d16-d9 signaling bits: the signaling bits in this register are the states of the received d9 to d16 bits in the receive signaling buffer. bit 7 is the d16 sig- naling bit value. please note that a receive signaling state is written into the sig- naling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit sec is written with a 0, zeros are written into the buffer for the ds0 ? s d-signaling bits. 18e - ch 1 28e - ch 2 38e - ch 3 48e - ch 4 7-0 receive signaling bits d24-d17 received d24-d17 signaling bits: the signaling bits in this register are the states of the received d17 to d24 in the receive signaling buffer. bit 7 is the d24 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit sec is written with a 0, zeros are written into the buffer for the ds0 ? s d-signaling bits. 1d0 - ch 1 2d0 - ch 2 3d0 - ch 3 4d0 - ch 4 7-0 transmit signaling bits a8-a1 transmit a8-a1 signaling bits: the signaling bits in this register are the a1 to a8 signaling bits written into the signaling buffer from the transmit signaling high- way. bit 7 is the a8 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is written with a 1.when the corresponding ds0 channel enable bit sec is written with a 0, the ability to insert transmit line robbed bit signaling bits from the transmit signaling buffer for the ds0 is disabled. 1d1 - ch 1 2d1 - ch 2 3d1 - ch 3 4d1 - ch 4 7-0 transmit signaling bits a16-a9 transmit a16-a9 signaling bits: the signaling bits in this register are the a9 to a16 signaling bits written into the signaling buffer from the transmit signaling highway. bit 7 is the a16 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit is written with a 0, the ability to insert transmit line robbed bit signaling bits from the transmit signaling buffer for the ds0 is disabled. address bit symbol description
- 134 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 1d2 - ch 1 2d2 - ch 2 3d2 - ch 3 4d2 - ch 4 7-0 transmit signaling bits a24-a17 transmit a24-a17 signaling bits: the signaling bits in this register are the a17 to a24 signaling bits written into the signaling buffer from the transmit signaling highway. bit 7 is the a24 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit is written with a 0, the ability to insert transmit line robbed bit signaling bits from the transmit signaling buffer for the ds0 is disabled. 1d4 - ch 1 2d4 - ch 2 3d4 - ch 3 4d4 - ch 4 7-0 transmit signaling bits b8-b1 transmit b8-b1 signaling bits: the signaling bits in this register are the b1 to b8 signaling bits written into the signaling buffer from the transmit signaling high- way. bit 7 is the b8 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit is written with a 0, the ability to insert transmit line robbed bit signaling bits from the transmit signaling buffer for the ds0 is disabled. 1d5 - ch 1 2d5 - ch 2 3d5 - ch 3 4d5 - ch 4 7-0 transmit signaling bits b16-b9 transmit b16-b9 signaling bits: the signaling bits in this register are the b9 to b16 signaling bits written into the signaling buffer from the transmit signaling highway. bit 7 is the b16 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit is written with a 0, the ability to insert transmit line robbed bit signaling bits from the transmit signaling buffer for the ds0 is disabled. 1d6 - ch 1 2d6 - ch 2 3d6 - ch 3 4d6 - ch 4 7-0 transmit signaling bits b24-b17 transmit b24-b17 signaling bits: the signaling bits in this register are the b17 to b24 signaling bits written into the signaling buffer from the transmit signaling highway. bit 7 is the b24 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit is written with a 0, the ability to insert transmit line robbed bit signaling bits from the transmit signaling buffer for the ds0 is disabled. 1d8 - ch 1 2d8 - ch 2 3d8 - ch 3 4d8 - ch 4 7-0 transmit signaling bits c8-c1 transmit c8-c1 signaling bits: the signaling bits in this register are the c1 to c8 signaling bits written into the signaling buffer from the transmit signaling high- way. bit 7 is the c8 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit is written with a 0, the ability to insert transmit line robbed bit signaling bits from the transmit signaling buffer for the ds0 is disabled. 1d9 - ch 1 2d9 - ch 2 3d9 - ch 3 4d9 - ch 4 7-0 transmit signaling bits c16-c9 transmit c16-c9 signaling bits: the signaling bits in this register are the c9 to c16 signaling bits written into the signaling buffer from the transmit signaling highway. bit 7 is the c16 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit is written with a 0, the ability to insert transmit line robbed bit signaling bits from the transmit signaling buffer for the ds0 is disabled. address bit symbol description
- 135 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 1da - ch 1 2da - ch 2 3da - ch 3 4da - ch 4 7-0 transmit signaling bits c24-c17 transmit c24-c17 signaling bits: the signaling bits in this register are the c17 to c24 signaling bits written into the signaling buffer from the transmit sig- naling highway. bit 7 is the c24 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit is written with a 0, the ability to insert transmit line robbed bit signaling bits from the transmit signaling buffer for the ds0 is disabled. 1dc - ch 1 2dc - ch 2 3dc - ch 3 4dc - ch 4 7-0 transmit signaling bits d8-d1 transmit d8-d1 signaling bits: the signaling bits in this register are the d1 to d8 signaling bits written into the signaling buffer from the transmit signaling high- way. bit 7 is the d8 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit is written with a 0, the ability to insert transmit line robbed bit signaling bits from the transmit signaling buffer for the ds0 is disabled. 1dd - ch 1 2dd - ch 2 3dd - ch 3 4dd - ch 4 7-0 transmit signaling bits d16-d9 transmit d16-d9 signaling bits: the signaling bits in this register are the d9 to d16 signaling bits written into the signaling buffer from the transmit signaling highway. bit 7 is the d16 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit is written with a 0, the ability to insert transmit line robbed bit signaling bits from the transmit signaling buffer for the ds0 is disabled. 1de - ch 1 2de - ch 2 3de - ch 3 4de - ch 4 7-0 transmit signaling bits d24-d17 transmit d24-d17 signaling bits: the signaling bits in this register are the d17 to d24 signaling bits written into the signaling buffer from the transmit sig- naling highway. bit 7 is the d24 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding ds0 channel enable bit sec is written with a 1. when the corresponding ds0 channel enable bit is written with a 0, the ability to insert transmit line robbed bit signaling bits from the transmit signaling buffer for the ds0 is disabled. address bit symbol description
- 136 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers frame bits the bits in the following read/write registers are the frame bits from the esf frame or the sf frame. address bit symbol description 130 - ch 1 230 - ch 2 330 - ch 3 430 - ch 4 7 fe2/fs4 received frame bit: this bit position is the received fe2 bit in the esf frame or the fs4 bit in the sf frame, and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 6 di/ft4 received frame bit: this bit position is the received fdl bit in the esf frame or the ft4 bit in the sf frame, and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 5 crc2/fs3 received frame bit: this bit position is the received crc2 bit (in frame 6) in the esf frame or the fs3 in the sf frame, and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 4di/ft3 received frame bit: this bit position is the received fdl bit in the esf frame or the ft3 bit in the sf frame, and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 3 fe1/fs2 received frame bit: this bit position is the received fe1 bit in the esf frame or the fs2 bit in the sf frame, and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 2di/ft2 received frame bit: this bit position is the received fdl bit in the esf frame or the ft2 bit in the sf frame, and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 1 crc1/fs1 received frame bit: this bit position is the received crc1 bit (in frame 2) in the esf frame or the fs1 bit in the sf frame, and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 0di/ft1 received frame bit: this bit position is the received fdl bit in the esf frame or the ft1 bit in the sf frame, and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip.
- 137 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 131 - ch 1 231 - ch 2 331 - ch 3 431 - ch 4 7 fe4/x received frame bit: this bit position is the received fe4 bit in the esf frame, but is unused in the sf format and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 6di/x received frame bit: this bit position is the received fdl bit in the esf frame, but is unused in the sf format and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 5 crc4/x received frame bit: this bit position is the received crc4 bit (in frame 14) in the esf frame, but is unused in the sf format and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 4di/x received frame bit: this bit position is the received fdl bit in the esf frame, but is unused in the sf format and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 3 fe3/fs6 received frame bit: this bit position is the received fe3 bit in the esf frame, or the fs6 bit in the sf frame, and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 2di/ft6 received frame bit: this bit position is the received fdl bit in the esf frame, or the ft6 bit in the sf frame, and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 1 crc3/fs5 received frame bit: this bit position is the received crc3 bit (in frame 10) in the esf frame, or the fs5 bit in the sf frame, and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 0di/ft5 received frame bit: this bit position is the received fdl bit in the esf frame, or the ft5 bit in the sf frame, and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. address bit symbol description
- 138 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 132 - ch 1 232 - ch 2 332 - ch 3 432 - ch 4 7 fe6/x received frame bit: this bit position is the received fe6 bit in the esf frame, but is unused in the sf format and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 6di/x received frame bit: this bit position is the received fdl bit in the esf frame, but is unused in the sf format and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 5 crc6/x received frame bit: this bit position is the received crc6 bit (in frame 22) in the esf frame, but is unused in the sf format and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 4di/x received frame bit: this bit position is the received fdl bit in the esf frame, but is unused in the sf format and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 3 fe5/x received frame bit: this bit position is the received fe5 bit in the esf frame, but is unused in the sf format and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 2di/x received frame bit: this bit position is the received fdl bit in the esf frame, but is unused in the sf format and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 1 crc5/x received frame bit: this bit position is the received crc5 bit (in frame 18) in the esf frame, but is unused in the sf format and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 0di/x received frame bit: this bit position is the received fdl bit in the esf frame, but is unused in the sf format and represents frame 1 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. address bit symbol description
- 139 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 133 - ch 1 233 - ch 2 333 - ch 3 433 - ch 4 7 fe2/fs4 received frame bit: this bit position is the received fe2 bit in the esf frame, or the fs4 bit in the sf frame, and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 6di/ft4 received frame bit: this bit position is the received fdl bit in the esf frame, or the ft4 bit in the sf frame, and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 5 crc2/fs3 received frame bit: this bit position is the received crc2 bit (in frame 6) in the esf frame, or the fs3 bit in the sf frame, and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 4di/ft3 received frame bit: this bit position is the received fdl bit in the esf frame, or the ft3 bit in the sf frame, and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 3 fe1/fs2 received frame bit: this bit position is the received fe1 bit in the esf frame, or the fs2 bit in the sf frame, and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 2di/ft2 received frame bit: this bit position is the received fdl bit in the esf frame, or the ft2 bit in the sf frame, and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 1 crc1/fs1 received frame bit: this bit position is the received crc1 bit (in frame 2) in the esf frame, or the fs1 bit in the sf frame, and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 0di/ft1 received frame bit: this bit position is the received fdl bit in the esf frame, or the ft1 bit in the sf frame, and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. address bit symbol description
- 140 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 134 - ch 1 234 - ch 2 334 - ch 3 434 - ch 4 7 fe4/x received frame bit: this bit position is the received fe4 bit in the esf frame, but is unused in the sf format and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 6di/x received frame bit: this bit position is the received fdl bit in the esf frame, but is unused in the sf format and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 5 crc4/x received frame bit: this bit position is the received crc4 bit (in frame 14) in the esf frame, but is unused in the sf format and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 4di/x received frame bit: this bit position is the received fdl bit in the esf frame, but is unused in the sf format and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 3 fe3/fs6 received frame bit: this bit position is the received fe3 bit in the esf frame, or the fs6 bit in the sf frame, and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 2di/ft6 received frame bit: this bit position is the received fdl bit in the esf frame, or the ft6 bit in the sf frame, and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 1 crc3/fs5 received frame bit: this bit position is the received crc3 bit (in frame 10) in the esf frame, or the fs5 bit in the sf frame, and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 0di/ft5 received frame bit: this bit position is the received fdl bit in the esf frame, or the ft5 bit in the sf frame, and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. address bit symbol description
- 141 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 135 - ch 1 235 - ch 2 335 - ch 3 435 - ch 4 7 fe6/x received frame bit: this bit position is the received fe6 bit in the esf frame, but is unused in the sf format and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 6di/x received frame bit: this bit position is the received fdl bit in the esf frame, but is unused in the sf format and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 5 crc6/x received frame bit: this bit position is the received crc6 bit (in frame 22) in the esf frame, but is unused in the sf format and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 4di/x received frame bit: this bit position is the received fdl bit in the esf frame, but is unused in the sf format and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 3 fe5/x received frame bit: this bit position is the received fe5 bit in the esf frame, but is unused in the sf format and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 2di/x received frame bit: this bit position is the received fdl bit in the esf frame, but is unused in the sf format and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 1 crc5/x received frame bit: this bit position is the received crc5 bit (in frame 18) in the esf frame, but is unused in the sf format and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. 0di/x received frame bit: this bit position is the received fdl bit in the esf frame, but is unused in the sf format and represents frame 2 that is written into the slip buffer. the bit is mapped onto the data highway with a delay of one frame and is not subject to a slip. address bit symbol description
- 142 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers hdlc link control registers the bits in the following read/write registers control the transmit and receive hdlc link that is carried in 4 d-bits, using th e f- bits in the esf format. address bit symbol description 108 - ch 1 208 - ch 2 308 - ch 3 408 - ch 4 7ehr enable hdlc receiver: a 1 enables the hdlc receiver. after flag detection and zero bit destuffing the bytes are written into the receive hdlc fifo. a 0 dis- ables the hdlc link controller, clears the fifo, and disables the hdlc receive interrupts. 6eht enable hdlc transmitter: a 1 enables the hdlc transmitter. the trans- mitter will send flags when the transmit hdlc fifo is empty. the bytes are formatted into the message when the fifo has bytes present. a 0 disables the hdlc link controller, clears the fifo, and disables the hdlc transmit interrupts. 5tab transmit abort: when set to 1, the transmit hdlc link controller will trans- mit the abort sequence (a zero followed by seven ones) after the next data byte. this is followed by clearing the transmit hdlc fifo, and sending con- tinuous flags. 4eom transmit end of message flag: when set to 1, the transmit hdlc fifo contains the last byte in the message. when the fifo has emptied, the 16- bit crc is transmitted, and this followed by an interrupt. 3 rhie receiver half full interrupt enable: this bit controls the receive hdlc status interrupt entry conditions for status bits rhis2-rhis0 (bits 7-5) in register x16h and event bits erhis2-erhis0 (bits 7-5) in register x0eh. when set to 1, the receive hdlc link controller generates an interrupt when the receive hdlc fifo is half full, or at the end of the message. when set to 0, the hdlc link controller generates an interrupt request only at the end of the message or when the fifo has overflowed. 2thie transmit half full interrupt enable: this bit controls the transmit hdlc status interrupt entry condition for status bit this (bit 4) in register x16h and event bit ethis (bit 4) in register x0eh. when set to 1, the transmit hdlc link controller generates an interrupt when the transmit hdlc fifo is half full, or at the end of the message. when set to 0, the hdlc link controller generates an interrupt request only at the end of the message or when the fifo has underflowed. 1 ebri enable bit code receiver interrupt: when the esf format is selected and this bit is set to 1, the bit code receive interrupt is enabled. 0ebt enable bit code transmitter: when the esf format is selected and this bit is set to 1, the bit code transmitter is enabled. the bit code defined in register x0bh is formatted into a 16-bit message that is transmitted continuously on the hdlc link as 1111111100000000.
- 143 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers hdlc link transmit and receive data registers two registers are used for writing the transmit bytes into the 16-byte transmit fifo, and for reading the receive bytes from the receive fifo, for the hdlc message. register x18h indicates the number of bytes in the receive fifo. all registers are read/write. address bit symbol description 10a - ch 1 20a - ch 2 30a - ch 3 40a - ch 4 7-0 thd7-thd0 hdlc transmit data: the byte written to this location is written to the transmit fifo. bit 0 corresponds to the first bit transmitted in the hdlc message byte. 10b - ch 1 20b - ch 2 30b - ch 3 40b - ch 4 7-6 r reserved: these bit locations do not exist. 5-0 tbcd5-tbcd0 transmit bit code data: the value written into this register will be formatted into a 16-bit message. the 16-bit message is transmitted continuously when control bit ebt is written with a 1 (bit 0 in register x08h) tbcd5 is the msb and the first bit in the code word transmitted (i.e., the six x bits in the 16-bit sequence 111111110xxxxxx0). 117 - ch 1 217 - ch 2 317 - ch 3 417 - ch 4 7-0 rhd7-rhd0 hdlc receive data: a read cycle transfers one byte from the receive fifo into this location. bit 0 corresponds to the first bit received in the hdlc message byte. 118 - ch 1 218 - ch 2 318 - ch 3 418 - ch 4 7-5 r reserved: disregard these bits. 4-0 c4-c0 hdlc receive fifo depth : this register indicates the number of data bytes currently present in the hdlc receive fifo. the value read is in binary. bit 0 is the lsb value. for example, the value 00000 indicates that the fifo is empty, and the value 01111 indicates that there are 15 bytes present in the receive fifo. 119 - ch 1 219 - ch 2 319 - ch 3 419 - ch 4 7-6 r reserved: disregard these bits. 5-0 rbcd5-rbcd0 receive bit code data : these bits are set to the bit code when a new bit code is received 8 out of 10 consecutive times. otherwise, these six bits are set to all ones. rbcd5 is the msb.
- 144 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers hdlc link status registers these registers are all read/write. the status bits in the x0e registers represent the latched status and interrupt request indications generated by the receive and transmit hdlc link controllers and the fifos. the latched event bits are a result of a receive or transmit status indication or interrupt request in the hdlc link status register x16h. the bits latch on either the positive transitions, the negative transitions, or both positive and negative transitions of the current status or interrupt request event bits as defined by the rise/fall control bits (bits 6 and 5) in the global configuration register 006h. a latched bit causes a hardware interrupt indication when the corresponding mask bit in the hdlc link mask reg- ister x0fh is written with a 0. the status bits in register x16h represent the current (unlatched) status and interrupt request indications generated by the receive and transmit hdlc link controllers and fifos. address bit symbol description 10e - ch 1 20e - ch 2 30e - ch 3 40e - ch 4 7-5 erhis2- erhis0 latched receive hdlc interrupt events: these latched status bits will change to indicate a corresponding change in rhis (2-0), bits 7-5 of register x16, except when rhis (2-0) changes to all zeros when these latched sta- tus bits will retain the previously latched value. these bits are cleared by writing a 0 to any bit position that is set. a hardware interrupt is generated when any of these bits latches and the corresponding mask bit position in register x0fh is written with a 0. 4ethis latched transmit hdlc interrupt event: the latched bit in this location corresponds to a transmit hdlc interrupt status indication in bit 4 in register x16h. this bit is cleared by writing a 0 to it. a hardware interrupt is gener- ated when this bit latches and the corresponding mask bit position in register x0fh is written with a 0. 3-2 erxfs1- erxfs0 latched receive hdlc fifo status events: these latched status bits will change to indicate a corresponding change in rxfs (1-0), bits 3-2 of register x16, except when rxfs (1-0) changes to all zeros when these latched status bits will retain the previously latched value. these bits are cleared by writing a 0 to any bit position that is set. if not masked by the cor- responding mask bit position in register x0fh, a hardware interrupt is gen- erated when any of these bits latches. 1-0 etxfs1- etxfs0 latched transmit hdlc fifo status events: these latched status bits will change to indicate a corresponding change in txfs (1-0), bits 1-0 of register x16, except when txfs (1-0) changes to all zeros when these latched status bits will retain the previously latched value. these bits are cleared by writing a 0 to any bit position that is set. a hardware interrupt is generated when this bit latches and the corresponding mask bit position in register x0fh is written with a 0.
- 145 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 10f - ch 1 20f - ch 2 30f - ch 3 40f - ch 4 7-5 mrhis2- mrhis0 receive hdlc interrupt mask: when one or more bits are set to a 1, the latched receive hdlc interrupt event indications in corresponding bits 7-5 in register x0eh are masked from causing a hardware interrupt. for example, if 001 is written into this location, a start of message indication is masked from causing a hardware interrupt (see rhis2-rhis0 below). 4mthis transmit hdlc interrupt mask: when set to 1, the latched transmit hdlc interrupt event indication corresponding to bit 4 in register x0eh is masked from causing a hardware interrupt. 3-2 mrxfs1- mrxfs0 receive hdlc fifo status interrupt mask: when one or more bits are set to a 1, a latched receive hdlc fifo event indication in corresponding bits 3-2 in register x0eh is masked from causing a hardware interrupt. for example, if a 01 is written into this location, a half full or more than half full indication is masked from causing a hardware interrupt (see rxfs1 - rxfs0 below). 1-0 mtxfs1- mtxfs0 transmit hdlc fifo status interrupt mask: when one or more bits are set to a 1, a latched transmit hdlc fifo event that has taken place in corre- sponding bits 1-0 in register x0eh is masked from causing a hardware inter- rupt. for example, if a 01 is written into this location, a half full or less than half full indication is masked from causing a hardware interrupt (see txfs1 - txfs0 below). address bit symbol description
- 146 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers 116 - ch 1 216 - ch 2 316 - ch 3 416 - ch 4 7-5 rhis2-rhis0 receive hdlc interrupt status: the following table lists the various interrupt status indications for the receive hdlc message. see control bit rhie (bit 3) in register x08h. rhis2 rhis1 rhis0 rhie condition 0 0 0 x idle condition. 0 0 1 x start of message indication. 0100valid message received (crc checked ok, message is 16 bytes or less), or fifo overflow. 0101fifo needs servicing (short message, receive half full control bit set) or valid message received. 0 1 1 x message received with crc error. 1 0 x x abort message detected. 1 1 x x bit code received (fifo automatically cleared). x represents either value may be indicated. 4this transmit hdlc interrupt status: a 1 indicates that the transmit fifo needs servicing, either because the message is completed, or because the fifo is equal to or less than half full. see control bit thie (bit 2) in register x08h. 3-2 rxfs1-rxfs0 receive fifo status: the following table lists the various receive fifo status indications for the receive hdlc message. rxfs1 rxfs0 condition 0 0 normal. fifo less than half full. 0 1 fifo equal to or more than half full. 1 0 fifo full. 1 1 fifo overflowed. 1-0 txfs1-txfs0 transmit fifo status: the following table lists the various transmit fifo status indications for the transmit hdlc message. txfs1 txfs0 condition 0 0 normal. fifo equal to or greater than half full. 0 1 fifo less than half full. 1 0 fifo overwritten (attempt to write to a full fifo). 1 1 fifo underflowed (attempt to read an empty fifo). address bit symbol description
- 147 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers ds0 loopback control registers these registers are all read/write. the control bits in the three registers are enabled when control bit ends0lb (bit 4 in register 0ffh) is written with a 1. writing a 1 to any one or more control bits in the following registers causes the corresponding ds0 channel(s) to be looped back from the receive path to the transmit path. the lbd24-lbd1 control bits are reset to 0 upon a hardware reset. address bit symbol description 11c - ch 1 21c - ch 2 31c - ch 3 41c - ch 4 7-0 lbd8-lbd1 loopback ds0 channels 8-1: a 1 in one or more control bits causes the corresponding ds0 channel(s) to be looped back. 11d - ch 1 21d - ch 2 31d - ch 3 41d - ch 4 7-0 lbd16-lbd9 loopback ds0 channels 16-9: a 1 in one or more control bits causes the corresponding ds0 channel(s) to be looped back. 11e - ch 1 21e - ch 2 31e - ch 3 41e - ch 4 7-0 lbd24-lbd17 loopback ds0 channels 24-17: a 1 in one or more control bits causes the corresponding ds0 channel(s) to be looped back.
- 148 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers application diagram the diagram in figure 45 illustrates the use of the qt1f- plus device to provide framing and ds0 access for a variety of ds1 sources. direct control of most commercial line interface unit devices (lius) is provided. note that these applications require operating the qt1f- plus at v dd = +5.0 volts to comply with the +5.0 volt parts connected to the qt1f- plus . figure 45. qt1f- plus TXC-03103C application qt1f- plus TXC-03103C 24 ds0+sig, clock & frame m13x txc-03305 ds3 qt1f- plus TXC-03103C qt1f- plus TXC-03103C } ds0 application } 2.048 mbit/s mvip: ds0, sig, clk, data cross point (ds0) cross point (ds0) ds1 liu liu ds1 ds1 ds1 ds1 ds1 temx8 txc-04218 sonet sts-3 phast-3n txc-06103 } ds0 application qt1f- plus TXC-03103C 24 ds0+sig, clock & frame
- 149 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers package information the qt1f- plus device is packaged in a 128-pin low profile plastic quad flat package suitable for surface mounting, as illustrated in figure 46 a. figure 46a. qt1f- plus TXC-03103C 128-pin package diagram see details ? b ? and ? c ? 102 65 39 38 1 128 pin #1 index d2 d1 d a a1 a2 see detail ? a ? note: dimensions in detail ? b ? detail ? c ? e1 ee2 c note: see figure 46b for package dimensions. e (typ) b detail ? a ? l l1 TXC-03103Cilq transwitch 103 64
- 150 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers notes: 1. linear dimension: millimeter. angular dimension: degree. 2. dimensions b and c do not include dambar protrusion. dambar cannot be located on the lower radius or the foot. 3. plating thickness included. plating thickness to be 0.005 mm minimum, 0.020 mm maximum. 4. dimensions d1 and e1 do not include mold protrusion or mold mismatch. 5. measured between centers of outer pins. figure 46b. qt1f- plus TXC-03103C 128-pin package dimensions symbol minimum nominal maximum note 1 a- -1.60 a1 0.05 - 0.15 a2 1.35 1.40 1.45 b 0.18 0.22 0.27 2, 3 c 0.10 - 0.20 2, 3 d 21.90 22.00 22.10 d1 19.90 20.00 20.10 4 d2 - 18.50 ref - 5 e 0.50 bcs e 15.90 16.00 16.10 e1 13.90 14.00 14.10 4 e2 - 12.50 ref - 5 l 0.45 0.60 0.75 l1 1.00 ref q0 -7
- 151 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers ordering information part number: TXC-03103Cilq 128-pin low profile plastic quad flat package related products txc-03305, m13x device (ds3/ds1 mux/demux). has built-in pmdl controller for a ds3 data link when in c-bit parity mode, integrated ds3/ds2/ds1 demultiplexing de-jitter buff- ers as additional features when compared to the m13e. can also operate in the m13e mode, when none of the additional features will be available. txc-04218, temx8 device (8 channel dual bus high density mapper). an add/drop multi- plexer, terminal multiplexer, and dual and single unidirectional ring applications. up to 8 e1, ds1, or vt/tu payloads are mapped to and from vt1.5/tu-11s and vt2/tu-12s carried in an stm-1 vc-4 or sts-3 format. txc-04222, temx28 ? device (28 channel dual bus high density mapper). an add/drop multiplexer, terminal multiplexer, and dual and single unidirectional ring applications. up to 28 e1, ds1, or vt/tu payloads are mapped to and from vt1.5/tu-11s and vt2/tu-12s carried in an stm-1 vc-4 or sts-3 format. txc-04251, qt1m device (quad ds1 to vt1.5 or tu-11 async mapper-desync). intercon- nects four ds1 signals with any four asynchronous mode vt1.5 or tu-11 tributaries carried in sonet sts-1 or sdh au-3 rate payload interface. txc-05427, cobra device (constant bit rate atm adaptation layer 1). provides atm aal1 structured and unstructured service for four t1, e1 or n x 64k constant bit rate inter- faces. txc-05870, packettrunk-4 device (tdmoip/mpls gateway). the packettrunk-4 device is a single-chip solution for implementing cost-effective, standards-compliant tdmoip/mpls interfaces and systems. packettrunk-4 provides all of the necessary interface, encapsulation, clock recovery, and qos functionality for enabling transport of unstructured or structured tdm signals over a packet-switched network (psn). txc-06103, phast ? -3n device (sonet stm-1/sts-3/sts-3c sdh/sonet overhead terminator with telecom bus interface). this device provides the combined functionality of the sot-3 and syn155c vlsi devices, with a telecom bus interface.
- 152 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute tel: (212) 642-4900 25 west 43 rd street fax: (212) 398-0023 new york, new york 10036 web: www.ansi.org the atm forum (u.s.a., europe, asia): 404 balboa street tel: (415) 561-6275 san francisco, ca 94118 fax: (415) 561-6120 web: www.atmforum.com atm forum europe office kingsland house - 5 th floor tel: 20 7837 7882 361-373 city road fax: 20 7417 7500 london ec1 1pq, england atm forum asia-pacific office hamamatsucho suzuki building 3f tel: 3 3438 3694 1-2-11, hamamatsucho, minato-ku fax: 3 3438 3698 tokyo 105-0013, japan bellcore (see telcordia) ccitt (see itu-t) eia (u.s.a.): electronic industries association tel: (800) 854-7179 (within u.s.a.) global engineering documents tel: (303) 397-7956 (outside u.s.a.) 15 inverness way east fax: (303) 397-2740 englewood, co 80112 web: www.global.ihs.com etsi (europe): european telecommunications standards institute tel: 4 92 94 42 00 fax: 4 93 65 47 16 650 route des lucioles web: www.etsi.org 06921 sophia-antipolis cedex, france go-mvip (u.s.a.): the global organization for multi-vendor integration protocol (go-mvip) tel: (800) 669-6857 (within u.s.a.) tel: (903) 769-3717 (outside u.s.a.) 3220 n street nw, suite 360 fax: (903) 769-3818 washington, dc 20007 web: www.mvip.org
- 153 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers ieee (corporate office): american institute of electrical engineers tel: (212) 419-7900 (within u.s.a.) 3 park avenue, 17th floor tel: (800) 678-4333 (members only) new york, new york 10016-5997 u.s.a. fax: (212) 752-4929 web: www.ieee.org itu-t (international): publication services of international telecommunication union tel: 22 730 5852 fax: 22 730 5853 telecommunication standardization sector web: www.itu.int place des nations, ch 1211 geneve 20, switzerland jedec (international): joint electron device engineering council tel: (703) 907-7559 2500 wilson boulevard fax: (703) 907-7583 arlington, va 22201-3834 web: www.jedec.org mil-std (u.s.a.): dodssp standardization documents ordering desk tel: (215) 697-2179 fax: (215) 697-1462 building 4 / section d web: www.dodssp.daps.mil 700 robbins avenue philadelphia, pa 19111-5094 pci sig (u.s.a.): pci special interest group tel: (800) 433-5177 (within u.s.a.) 5440 sw westgate dr., #217 tel: (503) 291-2569 (outside u.s.a.) portland, or 97221 fax: (503) 297-1090 web: www.pcisig.com telcordia (u.s.a.): telcordia technologies, inc. tel: (800) 521-2673 (within u.s.a.) attention - customer service tel: (732) 699-2000 (outside u.s.a.) 8 corporate place rm 3a184 fax: (732) 336-2559 piscataway, nj 08854-4157 web: www.telcordia.com ttc (japan): ttc standard publishing group of the telecommunication technology committee tel: 3 3432 1551 fax: 3 3432 1553 hamamatsu-cho suzuki building web: www.ttc.or.jp 1-2-11, hamamatsu-cho, minato-ku tokyo 105-0013, japan
- 154 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers list of data sheet changes this change list identifies those areas within this updated qt1f- plus TXC-03103C data sheet that have significant differences relative to the previous and now superseded qt1f- plus TXC-03103C data sheet: updated qt1f- plus TXC-03103C data sheet: preliminary ed. 3, october 2004 previous qt1f- plus TXC-03103C data sheet: preliminary ed. 2, march 2001 the page numbers indicated below of this updated data sheet include changes relative to the previous data sheet. page number of updated data sheet summary of the change all changed edition number and date. 1 added patent no. 6,456,595. updated trademark information. 20 changed conditions for parameter moisture exposure level and changed note 4 for ? absolute maximum ratings and environmental limitations ? table. 102 changed last sentence of description for symbol bdcst. 148 updated ? application diagram ? section. 151 updated ? related products ? section. 152 updated ? standards documentation sources ? section. 154 changed ? list of data sheet changes ? changes section.
- 155 of 156 - preliminary TXC-03103C-mb, ed. 3 october 2004 qt1f- plus TXC-03103C data sheet proprietary transwitch corporation information for use solely by its customers - notes - transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, software performance, or infringement of patents or services described herein. nor does transwitch warrant or repre- sent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of tran- switch covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. preliminary information documents con- tain information on products in the sampling, pre-production or early production phases of the product life cycle. characteristic data and other specifications are subject to change. contact transwitch applications engineering for current information on this product.
- 156 - transwitch corporation ? 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453

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